3.0 Registers
CX28394/28395/28398
3.16 System Bus Registers
Quad/x16/Octal—T1/E1/J1 Framers
TSIG_AB
TSIG_AB—AB Signaling. In T1 mode, only AB signaling bits are updated from TSIGI to the
TSIGn buffer. If SIGFRZ active, output CD signaling bits are copied from the buffered output
AB bits respectively. In E1 mode, setting TSIG_AB forces C = 0 and D = 1 when updating the
TSIGn buffer.
0 = ABCD signaling
1 = AB signaling
ASSIGN
Assign System Bus Time Slot—During T1 line applications where the system bus group
consists of 32 time slots, ASSIGN selects which 24 of 32 time slots are used to transport line
time slots. The number of assigned system bus time slots must always equal the number of line
time slots, therefore ASSIGN must be active in all 32 SBCn locations during E1 modes.
Unassigned time slots are not updated by the receiver as it fills the RSLIP buffer. T1 time slots
are filled sequentially from RSLIP 1 to 24. Time slots 0 and 25 to 31 are reserved for
unassigned values. Values are read from either the assigned or unassigned locations in a
sequential fashion based upon the ASSIGN bit. System bus output data for unassigned time
slots is taken from RSLIP buffer, which the processor can fill with any desired 16-bit fixed
value (8 bits in RSLIP_LO, plus 8 bits in RSLIP_HI).
0 = unassigned system bus time slot
1 = assigned system bus time slot
100–11F—Transmit Per-Channel Control (TPCn; n = 0 to 31)
7
6
5
4
3
2
1
0
TB7ZS/EMF-BIT
TLOOP
TIDLE
TLOCAL
TSIGA/TSIGO
TSIGB/RSIGO
TSIGC
TSIGD
TB7ZS/EMF-BIT
Bit7 Zero Code Substitution/Embedded F-bit Value (Applicable in T1 mode only)—For
assigned system bus time slots [ASSIGN; addr 0E0-0FF], TB7ZS replaces Bit 7 of the time
slot with a 1, if examination of 8-bit output detects all zeros. For an unassigned time slot where
TIDLE is active, EMF-BIT replaces all embedded F-bit outputs with the programmed
EMF-BIT value.
0 = no effect or force embedded F-bit (low)
1 = enable B7ZS or force embedded F-bit (high)
3-110
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
