3.0 Registers
CX28394/28395/28398
3.15 Data Link Registers
Quad/x16/Octal—T1/E1/J1 Framers
DL2[1: 0]
Data Link 2 Mode—Selects either HDLC formatted (FCS or Non-FCS) transmit and receive
data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC
modes, the transmit/receive circuits perform zero insertion/removal after each occurrence of 5
consecutive ones contained in the message bits. These include FLAG (0x7E) character
insertion/removal during idle channel conditions and ABORT (0xFF) code insertion/detection
upon errored channel conditions. Refer to ITU-T Recommendation Q.921 for complete details
of the HDLC link-layer protocol. FCS mode automatically generates, inserts, and checks the
16-bit Frame Check Sequence (FCS) without passing FCS bits through transmit and receive
FIFOs. While Non-FCS mode passes all message bits that exist between the opening and
closing FLAG characters through the FIFOs, without generating or checking FCS bits.
Non-FCS mode allows the processor to generate and check the entire contents of each HDLC
frame. Unformatted data link modes provide transparent channel access in which every data
link bit transmitted is supplied by the processor through TDL1, and each bit received is passed
to the processor through RDL2 [addr 0B3]. Pack8 and Pack6 unformatted mode options select
the number of bits per byte that are stored in transmit/receive FIFOs, eight or six bits,
respectively. The only data processing performed during unformatted mode is the alignment of
transmitted and received data bits with respect to the transmit/receive multiframe.
00 = FCS
01 = No FCS
10 = Pack8
11 = Pack6
TDL2_EN
RDL2_EN
Transmit Data Link 2 Enable—When enabled, the transmitter begins to empty and to format
the contents of the transmit data link FIFO for output during the selected time slot bits
according to the selected DL2[1:0] mode. Also enables generation of transmitter data link
interrupt events.
0 = disabled
1 = enable transmit data link
Receive Data Link 2 Enable—When enabled, the receiver begins to format data from the
selected time slot bits and to fill the receive data link FIFO according to the selected DL2[1:0]
mode. Also enables generation of receiver data link interrupt events.
0 = disabled
1 = enable receive data link
3-86
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
