3.0 Registers
CX28394/28395/28398
3.15 Data Link Registers
Quad/x16/Octal—T1/E1/J1 Framers
TMPTY1
Transmit FIFO Empty—Indicates no message data is present in transmit data link FIFO. This
is typically checked by the processor in response to a TMSG or TNEAR interrupt. If this is a
TMSG interrupt, the processor checks TMPTY1 to determine that all queued messages were
sent (TMPTY1=1) or more queued messages remain to be sent (TMPTY1=0). If this is a
TNEAR interrupt, the processor confirms TMPTY1=0 to verify the partial transmit message
was not aborted by a FIFO underrun.
0 = FIFO contains data to be transmitted
1 = FIFO empty
TNEAR1
TFULL1
Transmit FIFO Near Empty—Indicates data link has emptied transmit FIFO to below the near
empty threshold specified in FEC[5:0]. After sending the byte that occupied the near empty
FIFO threshold level, TNEAR1 goes active high, which generates a TNEAR interrupt. The
processor must write data to TDL1 to fill the transmit FIFO beyond the near empty threshold
in order to clear TNEAR1 status and enable the next TNEAR interrupt event.
0 = FIFO depth is below the near empty level
1 = FIFO has been emptied past the near empty level
Transmit FIFO Full—Indicates processor has completely filled 64 byte locations in transmit
FIFO. While TFULL1 remains active, any subsequent processor writes to TDL1 are ignored. If
the processor should inadvertently write to TDL1 while TFULL1 is active, the processor must
allow FIFO to become completely empty without writing to TDL1_EOM in order to force the
transmitter to send an Abort character.
0 = FIFO is less than full
1 = FIFO has been completely filled
0AF—DL2 Time Slot Enable (DL2_TS)
7
6
5
4
3
2
1
0
DL2_TS[7]
DL2_TS[6]
DL2_TS[5]
DL2_TS[4]
DL2_TS[3]
DL2_TS[2]
DL2_TS[1]
DL2_TS[0]
DL2_TS[7]
Unchannelized—Test mode only; all time slots selected. Zero for normal operation.
DL2_TS[6, 5]
Frame Select—Transmit and receive data link 2 operates on data only during the specified
T1/E1 frames. Frame select options give the processor access to different types of data link
channels, as well as overhead channels. Overhead bit insertion is performed after TDL2, so
internal transmitter overhead insertion must be bypassed [TFRM; addr 072] before the
processor supplied overhead can be output from TDL2.
00 = all frames
01 = even frames only
10 = odd frames only
11 = Not valid
3-84
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
