CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.15 Data Link Registers
0AC—TDL #1 End Of Message Control (TDL1_EOM)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
EOM[7]
EOM[6]
EOM[5]
EOM[4]
EOM[3]
EOM[2]
EOM[1]
EOM[0]
TDL1_EOM
End of Transmit Message. Writing any data value to TDL1_EOM marks the last byte of data
written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or
marks the end of a transmit circular buffer. Processor must write TDL1_EOM after writing a
complete message or the last byte of a circular buffer into TDL1 [addr 0AD]. The written data
value is ignored and cannot be read back. Multiple HDLC messages are allowed to be queued
in the transmit FIFO simultaneously. In addition, the transition from one circular buffer to
another occurs only after the end of message byte of the current circular buffer has been sent.
0AD—Transmit Data Link FIFO #1 (TDL1)
7
6
5
4
3
2
1
0
TDL1[7]
TDL1[6]
TDL1[5]
TDL1[4]
TDL1[3]
TDL1[2]
TDL1[1]
TDL1[0]
TDL1[7:0]
Transmit Message Data—Output by the transmitter data link, from LSB to MSB, and sent on
the selected time slot bits. Processor writes 8-bit FIFO data during HDLC and Pack8 modes.
During Pack6 mode, only the six least significant bits TDL1[5:0] are used.
0AE—TDL #1 Status (TDL1_STAT)
7
6
5
4
3
2
1
0
—
—
—
—
TMSG1
TMPTY1
TNEAR1
TFULL1
TMSG1
In Progress Transmit Message—The real time status of the transmit message sequencer is
provided mostly for diagnostic purposes. During HDLC modes, TMSG1 is high for the
interval between opening and closing FLAG characters. This indicates that transmitter is
actively pulling data bytes from transmit FIFO locations. TMSG1 is low while the channel
transmits FLAG or Abort characters. During unformatted and circular buffer modes, TMSG1
is high continuously.
0 = channel idle
1 = channel actively emptying FIFO
100054E
Conexant
3-83
CONEXANT [ CONEXANT SYSTEMS, INC ]
