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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX28394/28395/28398  
3.0 Registers  
Quad/x16/OctalT1/E1/J1 Framers  
3.15 Data Link Registers  
DL2_TS[4:0]  
Time Slot Word Enable—Transmit and receive data link 2 operates on data only during the  
specified time slot. During T1 mode, selecting time slot zero enables data link operation on the  
F-bit positions.  
DL2_TS[4:0]  
00000  
00001  
|
Time Slot Enable  
F-bit (T1) or TS0 (E1)  
TS1  
|
11110  
11111  
TS30  
TS31  
0B0DL2 Bit Enable (DL2_BIT)  
7
6
5
4
3
2
1
0
DL2_BIT[7]  
DL2_BIT[6]  
DL2_BIT[5]  
DL2_BIT[4]  
DL2_BIT[3]  
DL2_BIT[2]  
DL2_BIT[1]  
DL2_BIT[0]  
DL2_BIT[7:0]  
DL2 Bit Select—Works in conjunction with DL2_TS [addr 0AF] to select one or more time  
slot bits for data link input and output. Any combination of bits may be enabled by writing the  
corresponding DL2_BIT active (high). The LSB enables the first bit transmitted or received,  
and MSB enables eighth bit transmitted or received. DL2_BIT has no effect when DL2_TS  
selects T1 F-bits.  
0 = disable data link bit  
1 = enable data link bit  
0B1DL2 Control (DL2_CTL)  
Unused bits are reserved and should be written to 0.  
7
6
5
4
3
2
1
0
TDL2_RPT  
DL2[1]  
DL2[0]  
TDL2_EN  
RDL2_EN  
TDL2_RPT  
Circular Transmit Buffer Enable—Processor can fill transmit FIFO [TDL2; addr 0B8] with up  
to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be sent repeatedly. While  
TDL2_RPT is active high, data written to TDL2 is held until the processor writes an end of  
message [TDL2_EOM; addr 0B7]. After TDL2_EOM is written, the transmitter waits for the  
beginning of the next output multiframe (based on the selected transmit framing mode) before  
sending the first byte of the circular buffer. Subsequent bytes are output in the selected time  
slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the  
processor writes new buffer data and another TDL2_EOM. This allows the processor to send  
multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS, or CAS overhead bits.  
0 = normal transmit FIFO  
1 = enable circular transmit buffer  
100054E  
Conexant  
3-85  
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