CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.5 Interrupt Status Registers
3.5 Interrupt Status Registers
An Interrupt Status Register (ISR) bit is latched active (high) whenever its corresponding interrupt source
reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt
enable is active (high), each interrupt event forces the associated IRR bit active (high). Interrupt sources fall into
two categories:
• Rising-edge source reports an interrupt event when status changes from inactive to active state. Unless
specifically noted otherwise, all ISR bits are rising-edge sources.
• Dual-edge source reports an interrupt event when status changes from inactive to active (rising edge), or
from active to inactive (falling edge). The processor must read the associated real-time status to determine
which edge occurred.
Interrupt events are reported in real time in the MIR register and on the INTR* output pin if interrupt enable
is active (high). Otherwise, the interrupt status is latched and reported according to the selected latching mode
[LATCH; addr 046] without asserting the MIR bit or the INTR* output pin. Table 3-6 summarizes the interrupt
status registers.
Table 3-6. Interrupt Status Register Summary
004
ISR7
ALARM1
005
ISR6
ALARM2
006
ISR5
ERROR
007
ISR4
COUNT
008
ISR3
TIMER
009
ISR2
DL1
00A
ISR1
DL2
00B
ISR0
PATT
Bit
0
1
2
3
4
5
6
7
SIGFRZ
RLOF
ONESEC
TLOF
FERR
MERR
SERR
CERR
—
FERR[12]
CRC[10]
LCV[16]
FEBE[10]
BERR[12]
SEF[2]
RFRAME
RMF
TMSG
TNEAR
TEMPTY
TDLERR
RMSG
TMSG
TNEAR
TEMPTY
TDLERR
RMSG
RNEAR
RFULL
RBOP
TFERR
TMERR
TSERR
TCERR
PSYNC
BSLIP
—
RLOS
—
RMSYNC
RSIG
RALOS
RAIS
TLOC
—
TFRAME
TMF
RPDV
RYEL
TPDV
LOOPUP
LOOPDN
—
RNEAR
RFULL
TBOP
RSLIP
TSLIP
COFA[2]
FRED[4]
TMSYNC
TSIG
RMYEL
—
100054E
Conexant
3-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
