CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.5 Interrupt Status Registers
007—Counter Overflow Interrupt Status (ISR4)
All count overflow events in ISR4 are from rising edge sources. Each event is latched active high when the
respective error counter [addr 050–05A] reaches its maximum count value, but only while the respective IER4
[addr 00F] interrupt enable bit is active. If the corresponding interrupt is masked, then no overflow status is
reported. Active overflow status bits are held until the processor read clears ISR4. Each event triggers an
interrupt if the corresponding IER4 bit is enabled.
7
6
5
4
3
2
1
0
FRED[4]
COFA[2]
SEF[2]
BERR[12]
FEBE[10]
LCV[16]
CRC[10]
FERR[12]
FRED[4]
Out of Frame Error Count Overflow
Change of Alignment Count Overflow
Severely Errored Frame Count Overflow
Test Pattern Bit Error Count Overflow
FEBE Error Count Overflow
COFA[2]
SEF[2]
BERR[12]
FEBE[10]
LCV[16]
CRC[10]
FERR[12]
LCV (BPV+EXZ) Error Count Overflow
CRC6/CRC4 Error Count Overflow
Ft/Fs/FPS/FAS Error Count Overflow
008—Timer Interrupt Status (ISR3)
All events in ISR3 are from rising edge sources. Each event is latched active high and held until the processor
read clears ISR3. Each event triggers an interrupt if corresponding IER3 bit is enabled [addr 010].
7
6
5
4
3
2
1
0
TSIG
TMSYNC
TMF
TFRAME
RSIG
RMSYNC
RMF
RFRAME
TSIG
Transmit Signaling Multiframe—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms
(CAS) coincident with the first bit of a transmit signaling multiframe.
0 = no timer event
1 = transmit signaling multiframe
TMSYNC
TMF
TX System Bus MF Sync—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (CAS)
coincident with the first bit of transmit system bus multiframe input on TPCMI.
0 = no timer event
1 = TSB multiframe
Transmit Multiframe—TMF is activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (MFAS)
coincident with the first bit of a transmit multiframe.
0 = no timer event
1 = transmit multiframe
TFRAME
Transmit Frame—Activated every 193 bits (T1) or 256 bits (E1) coincident with first bit of a
transmit frame. Processor may read TPHASE [addr ODC] to determine which TSLIP buffer
half can be accessed.
0 = no timer event
1 = transmit frame
100054E
Conexant
3-19
CONEXANT [ CONEXANT SYSTEMS, INC ]
