3.0 Registers
CX28394/28395/28398
3.5 Interrupt Status Registers
Quad/x16/Octal—T1/E1/J1 Framers
006—Error Interrupt Status (ISR5)
All events in ISR5 are from rising edge sources. Each event is latched active high and held according to the
LATCH_ERR bit [addr 046] and triggers an interrupt if the corresponding IER5 bit is enabled [addr 00E].
7
6
5
4
3
2
1
0
TSLIP
RSLIP
—
—
CERR
SERR
MERR
FERR
TSLIP
Transmit Slip Error—Two types of TSLIP buffer errors are reported: TFSLIP or TUSLIP.
Error type is reported separately in slip status [SSTAT; 0D9].
0 = no error
1 = TSLIP error
RSLIP
CERR
Receive Slip Error—Two types of RSLIP buffer errors are reported: RFSLIP or RUSLIP. Error
type is reported separately in slip status [SSTAT; 0D9].
0 = no error
1 = RSLIP error
CRC6/CRC4 Block Error—Applicable to ESF and MFAS modes only, read zero in other
modes. CERR indicates one or more bit errors found in received CRC-6 or CRC-4 checksum
block pattern.
0 = no error
1 = CRC error
SERR
MERR
FERR
CAS Pattern Error—Applicable only in E1 mode, read zero in T1 mode. SERR indicates one
or more bit errors in received TS16 Multiframe Alignment Signal (MAS).
0 = no error
1 = CAS error
MFAS Pattern Error—Applicable only in E1 mode (read zero in T1 mode)—Indicates one or
more bit errors in received MFAS alignment pattern.
0 = no error
1 = MFAS error
Frame Error—Ft/Fs/T1DM/FPS/FAS Pattern Error—Indicates one or more Ft/Fs/FPS frame
bit errors or FAS pattern errors. Refer to Tables A-1 through A-6 for a description of which
frame bits are monitored according to the selected receive framer mode.
0 = no error
1 = frame error
3-18
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
