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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX28394/28395/28398  
3.0 Registers  
Quad/x16/OctalT1/E1/J1 Framers  
3.4 Interrupt Control Register  
3.4 Interrupt Control Register  
003—Interrupt Request Register (IRR)  
An IRR bit is latched active (high) whenever an enabled interrupt source reports an interrupt event in the  
corresponding Interrupt Status Register [ISR7–ISR0; addr 004–00B]. IRR is latched until the corresponding  
ISR register is read by the processor. Reading ISR clears the respective IRR bit, independent of clearing ISR  
bits. Therefore, persistently active ISR bits won't affect INTR* deactivation. All IRR bits are logically OR'ed to  
activate a corresponding MIR bit and INTR*, so the processor must read IRR = 00 before exiting its interrupt  
service routine in order to confirm the MIR bit has been deasserted.  
7
6
5
4
3
2
1
0
ALARM1  
ALARM2  
ERROR  
COUNT  
TIMER  
DL1  
DL2  
PATT  
ALARM1  
Alarm 1 Interrupt Request—Indicates one or more receiver errors. Processor reads ISR7 [addr  
004] to locate specific source.  
0 = no event  
1 = active interrupt request  
ALARM2  
Alarm 2 Interrupt Request—Indicates one-second timer expiry, or detection of one or more  
transmitter errors, or detection of inband loopback codeword. Processor reads ISR6 [addr 005]  
to locate specific source.  
0 = no event  
1 = active interrupt request  
ERROR  
COUNT  
TIMER  
Error Interrupt—Indicates one or more errors detected by receive framer, RSLIP, or TSLIP  
circuits. Processor reads ISR5 [addr 006] to locate specific source.  
0 = no event  
1 = active interrupt request  
Counter Overflow Interrupt—Indicates one or more error counts [addr 050–05A] have issued  
an overflow interrupt. Processor reads ISR4 [addr 007] to locate specific source.  
0 = no event  
1 = active interrupt request  
Timer Interrupt Request—Indicates that the transmit, receive, or system bus timebase has  
reached a frame count terminus or that the receive signaling stack [STACK; addr 0DA] has  
been updated with new signaling during the prior multiframe. Processor reads ISR3 [addr 008]  
to locate specific source.  
0 = no event  
1 = active interrupt request  
DL1  
Data Link Controller 1 or BOP Transmit—Indicates that a transmit or receive interrupt issued  
by DL1 or BOP transceiver has begun transmitting a priority codeword from TBOP  
[addr 0A1]. Processor reads ISR2 [addr 009] to locate specific source.  
0 = no event  
1 = active interrupt request  
100054E  
Conexant  
3-13