CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2 PCI Configuration Registers
2.2 PCI Configuration Registers
2.2.1 Function 0 Network Controller—PCI Master and Slave
MUSYCC provides the necessary configuration space for a PCI bus controller to
query and configure MUSYCC’s PCI interface. PCI configuration space consists
of a device-independent header region (64 bytes) and a device-dependent header
region (192 bytes). MUSYCC provides the device-independent header section
only. Access to the device-dependent header region results in 0s being read, with
no effect on writes.
There are three types of registers available in MUSYCC:
1. Read-Only (RO): Returns a fixed bit pattern if the register is used, or a 0 if
the register is unused or reserved.
2. Read-Resettable (RR): Can be reset to 0 by writing a 1 to the register.
3. Read/Write (RW): Retains the value last written to it.
MUSYCC’s Function 0 PCI Configuration Space has 16 dword registers.
Tables 2-3 through 2-9 define these registers.
Register 0, Address 00h
Table 2-3. Register 0, Address 00h
Bit
Reset
Value
Name
Field
Type
Description
Device ID(1)
31:16
15:0
847xh
RO
This unique device identification is assigned by the
manufacturer. This field always returns the value 847xh where x
can be 1, 2, 4, or 8 depending on the 32, 64, 128, or 256 channel
version of the device, respectively.
Vendor ID(1)
14F1h
RO
The unique vendor identification assigned to the manufacturer.
This field always returns the value 14F1h.
NOTE(S):
(1)
Registers shared between Function 0 and 1.
100660E
Conexant
2-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
