2.0 Host Interface
CN8478/CN8474A/CN8472A/CN8471A
2.2 PCI Configuration Registers
Multichannel Synchronous Communications Controller (MUSYCC™)
Register 1, Address 04h
The Status register records status information for PCI bus related events. The
Command register provides coarse control to generate and respond to PCI
commands.
At reset, MUSYCC sets the bits in this register to 0, meaning MUSYCC is
logically disconnected from the PCI bus for all cycle types except configuration
read and configuration write cycles.
Table 2-4. Register 1, Address 04h (1 of 2)
Bit
Field
Reset
Value
Name
Type
RR
Description
31
Status
0
Detected Parity Error. This bit is set by MUSYCC whenever it
detects a parity error on a data phase when MUSYCC is a target,
even if parity error response is disabled.
30
29
28
0
0
0
RR
RR
RR
Detected System Error. This bit is set by MUSYCC whenever it
asserts SERR*.
Received Master Abort. This bit is set by MUSYCC whenever a
MUSYCC-initiated cycle is terminated with master-abort.
Received Target Abort. MUSYCC sets this bit when a
MUSYCC-initiated cycle is terminated by a target-abort.
27
0
RO
RO
Unused.
26:25
01b
DEVSEL* Timing. Indicates MUSYCC is a medium-speed PCI
device. This means the longest time it will take MUSYCC to
return DEVSEL* when it is a target of 3 clock cycles.
24
23
0
RR
RO
Data Parity Detected. MUSYCC sets this bit when three
conditions are met:
1. MUSYCC asserts PERR* or observes PERR*.
2. MUSYCC is the master for that transaction.
3. The Parity Error Response bit in this register is set.
1b
Fast Back-to-Back Capable. Read Only. Indicates that when
MUSYCC is a target, it is capable of accepting fast back-to-back
transactions when the transactions are not to the same agent.
22
21
0
I
RO
RO
Unused.
Indicates the device is 66 MHz capable. This bit is set by
Revision C and later devices.
20:16
0
RO
Unused.
2-8
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
