CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2 PCI Configuration Registers
Table 2-4. Register 1, Address 04h (2 of 2)
Bit
Field
Reset
Value
Name
Command
Type
RO
Description
15:10
0
0
0
Unused.
9
8
RW
RW
Fast back-to-back mode is not supported.
SERR* enable.
If 1, disables MUSYCC’s SERR* driver.
If 0, enables MUSYCC’s SERR* driver and allows reporting of
address parity errors.
7
6
0
0
RO
Wait cycle control. MUSYCC does not support address stepping.
RW
Parity error response. This bit controls MUSYCC’s Function 0
response to parity errors.
If 1, MUSYCC takes normal action when a parity error is
detected on a cycle with Function 0 as the target.
If 0, MUSYCC ignores parity errors.
5
4
0
0
RO
RO
VGA palette snoop. Unused.
Memory write and invalidate. The only write cycle type MUSYCC
generates is memory write.
3
2
0
0
RO
Special cycles. Unused. MUSYCC ignores all special cycles.
RW
Bus master.
If 1, MUSYCC is permitted to act as bus master.
If 0, MUSYCC is disabled from generating PCI accesses.
1
0
RW
Memory space. Access control.
If 1, enables MUSYCC to respond to Function 0 memory
space access cycles.
If 0, disables MUSYCC’s response.
0
0
RO
I/O space accesses. MUSYCC does not contain any I/O space
registers.
NOTE(S): An active-low signal is denoted by a trailing asterisk (*).
100660E
Conexant
2-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
