CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.1 PCI Interface
2.1.2 PCI Bus Operations
MUSYCC behaves either as a PCI master or a PCI slave at any time and switches
between these modes as required during device operation.
As a PCI slave, MUSYCC responds to the following PCI bus operations:
•
•
•
•
•
•
•
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple (treated like Memory Read in slave mode)
Memory Read Line (treated like Memory Read in slave mode)
Memory Write and Invalidate (treated like Memory Write)
All other PCI cycles are ignored by MUSYCC. Only memory cycles are
mapped to operations on the EBUS.
As a PCI-master, MUSYCC generates the following PCI bus operations:
•
•
•
Memory Read Multiple (generated only in master mode)
Memory Write
Dual Address Cycle
2.1.3 PCI Configuration Space
This section describes how MUSYCC implements the required PCI configuration
register space to provide configuration registers. These registers satisfy the needs
of current and anticipated system configuration mechanisms, without specifying
those mechanisms or otherwise placing constraints on their use. The
configuration registers provide the following functions:
•
•
•
Full device relocation, including interrupt binding
Installation, configurations, and booting without user intervention
System address map construction by device-independent software
MUSYCC responds only to Type 0 configuration cycles. Type 1 cycles, which
pass a configuration request on to another PCI bus, are ignored.
MUSYCC is a two-function PCI agent; therefore, it must implement
configuration space for both functions.
The PCI controller in MUSYCC responds to configuration and memory
cycles, but only memory cycles cause bus activity on the EBUS.
100660E
Conexant
2-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
