2.0 Host Interface
CN8478/CN8474A/CN8472A/CN8471A
2.1 PCI Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
The address phase during a MUSYCC configuration cycle indicates the
function number and register number being addressed which can be decoded by
observing the status of the address lines AD[31:0]. Figure 2-2 shows the address
lines during the configuration cycle.
Figure 2-2. Address Lines During Configuration Cycle
Bit
Number
31
11 10
8 7
2 1
0
Don't
Care
3-Bit
Function
Number
6-Bit
Register
Number
2-Bit
Type
Number
(2)
(1)
(3)
NOTE(S):
(1)
MUSYCC supports Functions 0 and 1.
MUSYCC supports Registers 0 through 15, inclusive.
MUSYCC supports Type 0 configuration cycles.
(2)
(3)
The value of the signal lines AD[10:8] selects the function being addressed.
MUSYCC supports Functions 0 and 1 and will not respond if another function is
selected.
The value of the signal lines AD[7:2] during the address phase of
configuration cycles selects the register of the configuration space to access.
Valid values are 0–15. Accessing registers outside this range results in an all 0s’
value being returned on reads, and no action being taken on writes.
The value of the signal lines AD[1:0] must be 00b for MUSYCC to respond. If
these bits are 0 and the IDSEL signal line is asserted, then MUSYCC will respond
to the configuration cycle.
Although there are two separate configuration spaces, one for Function 0 and
one for Function 1, some internal registers are shared between the two spaces.
The Base Code register contains the Class Code, Sub Class Code, and
Register Level Programming Interface registers. Tables 2-1 and 2-2 list
Function 0 and Function 1 configuration spaces.
2-4
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
