2.0 Host Interface
CN8478/CN8474A/CN8472A/CN8471A
2.1 PCI Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
In summary, both configuration spaces have unique registers except for the
Device ID, Vendor ID, and Revision ID, which are shared between the
configuration spaces for Functions 0 and 1.
MUSYCC is a multifunction device with two sources of interrupts: the HDLC
controller interrupts and the expansion bus physical layer interrupts. MUSYCC
uses the INTA* pin for HDLC controller interrupts and the INTB* pin for
interrupts generated by devices on the expansion bus connected to the EINT* pin.
All writable bits in the configuration space are reset to 0 by the hardware
reset, PRST* asserted. After reset, MUSYCC is disabled and responds only to
PCI configuration write and PCI configuration read cycles. Write cycles to
reserved bits and registers have no effect. Read cycles to reserved bits always
result in 0 being read.
2-6
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
