1.0 System Description
CN8478/CN8474A/CN8472A/CN8471A
1.1 Pin Descriptions
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 1-4. CN8478 Hardware Signal Definitions (6 of 6)
MQFP
Pin No.
Pin Label
Signal Name
JTAG Clock
I/O
Definition
35
TCK
I
I
Clock in the TDI and TMS signals and clock out TDO signal.
36
TRST*
JTAG Reset
An active-low input that resets the JTAG state machine. This pin
should be pulled low in normal operation.
37
TMS
TDO
TDI
JTAG Mode Select
JTAG Data Output
JTAG Data Input
Test Mode
I
The test signal input decoded by the TAP controller to control
test operations.
38
t/s O The test signal that transmits serial test instructions and tests
data.
39
I
The test signal that receives serial test instructions and tests
data.
112-114
TM[0]
TM[1]
TM[2]
I
Encodes test modes.
These pins have internal pull-downs and may be left open by
the system designer.
TM[0]
TM[1]
TM[2]
0
1
0
1
0
1
Normal Operation. Tie to ground.
All outputs three-stated.
(2)
(3)
VDDc
Power
–
–
19 pins are provided for power. Four VDDc (core), four VDDi
(input), nine VDDo (output), and two VGG (5 V-tolerant supply).
The VDDc require 2.5 V +/- 5%, the VDDi and VDDo require 3.3 V
+/- 5%, and the VGG require 5 V +/- 5%. The recommended
power ramp sequence is VDDi and VDDo together, then VDDc at
VDDi(3)
VDDo
VGG
t = 0+. VGG can be powered at any time.
VSS(3)
VSSo
Ground
27 pins are provided for ground, 0 V DC. 10 VSS (core and input)
and 17 VSSo (output).
NOTE(S):
(1)
These pins have internal pullups and may be left open by the system designer.
VDDc Pin Numbers: 27, 77, 132, 185
(2)
VDDi Pin Numbers: 13, 67, 118, 171
VDDo Pin Numbers: 42, 63, 81, 95, 110, 147, 164, 181, 201
VGG Pin Numbers: 52, 156
VSS Pin Numbers: 14, 28, 53, 68, 78, 119, 133, 157, 172, 186
VSSo Pin Numbers: 44, 55, 64, 73, 82, 89, 96, 104, 111, 137, 148, 153, 165, 175, 182, 191, 202
An active low signal is denoted by a trailing asterisk (*).
(3)
(4)
1-24
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
