Bt860/861
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Multiport YCrCb to NTSC/PAL /SECAM
Register 10–11
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
10
11
00
HSYNC_OFF[7:0]
00
Reserved
HSYNC_OFF[9:8]
Reserved bits should be set to zero when written and will return zero when read.
HSYNC_OFF[9:0]
HSYNC* Offset
Defines the offset in system clocks of HSYNC* pulse relative to the internal horizontal
sync in master mode.
This value is twos complement so that:
000 = 0 clock delay
1FF = 2047 clock delay
200 = 2048 clock advance
3FF = 1 clock advance
Register 12
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
12
02
HSYNC_WIDTH[7:0]
HSYNC_WIDTH[7:0]
HSYNC* Width
Width in system clocks of HSYNC* pulse in master mode.
Register 13–15
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
13
14
15
8C
AF
0F
PLL_FRACT[7:0]
PLL_FRACT[15:8]
PLL_FRACT [18:16]
PLL_INT[4:0]
PLL_FRACT[18:0]
PLL_INT[4:0]
Fractional Portion of the PLL Multiplier
Integer Portion of the PLL Multiplier
The range of the PLL multiplier is from 0.0 to 3.999999, and the minimum adjustment is
1.90734863 × 10–6
.
The equation to derive PLL frequency is:
Desired PLL frequency = [(XTAL freq / 8) × (PLL_INT + (PLL_FRACT / 219))]
D860DSA
Conexant
5-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
