5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 02
Default
Value
Register
02
D7
D6
D5
D4
D3
D2
D1
D0
04
FIELD_CNT[3:0]
VLOCK_ERR
PLL_LOCK FIFO_UNDER FIFO_OVER
This register is read only.
FIELD_CNT[3:0]
Field Number
000 indicates the first field.
VLOCK_ERR
PLL_LOCK
VID Port Locking Status
High if VID port input frequency exceeds tracking range, as programmed by LC_MAXOFF.
PLL Lock Status Bit
0 = Unable to lock to desired PLL frequency.
1 = PLL is able to lock to desired frequency.
FIFO_UNDER
FIFO_OVER
FIFO Underflow Status
High if VID port FIFO underflows. Resets to zero on write.
FIFO Overflow Status
High if VID port FIFO overflows. Resets to zero on write.
Register 04–05
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
04
05
B4
HCLK[7:0]
06
Reserved
HCLK[11:8]
Reserved bits should be set to zero when written and will return zero when read.
HCLK[11:0]
Number of System Clocks Per Line
Register 06–07
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
06
07
C8
02
HACTIVE[7:0]
Reserved
HACTIVE[9:8]
Reserved bits should be set to zero when written and will return zero when read.
HACTIVE[9:0] Number of Active Pixels Per Line
5-14
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
