Bt860/861
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Multiport YCrCb to NTSC/PAL /SECAM
Register 19
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
19
80
PCLK_SEL
VSYNCI
HSYNCI
FIELDI
BLANKI
BLK_IGNORE PCLK_EDGE
FLDMODE
PCLK_SEL
Pixel Clock (system clock) Select
State of FIELD pin during power-up determines the default value of PCLK_SEL. FIELD = 1
corresponds to PCLK_SEL = 0 as default, while FIELD = 0 corresponds to PCLK_SEL = 1 as
default. If FIELD is not externally loaded, an internal pull-down sets FIELD = 0 at power-up.
0 = Use CLKIN as pixel clock source.
1 = Use PLL as pixel source (derived from XTI and XTO inputs).
VSYNCI
HSYNCI
FIELDI
VSYNC* Polarity Control
0 = Active low VSYNC* pin.
1 = Active high VSYNC* pin.
HSYNC* Polarity Control
0 = Active low HSYNC* pin.
1 = Active high HSYNC* pin.
FIELD Polarity Control
0 = A 1 on FIELD pin indicates an even field.
1 = A 1 on FIELD pin indicates an odd field.
BLANKI
BLANK* Polarity Control
0 = Active low BLANK* pin.
1 = Active high BLANK* pin.
BLK_IGNORE
Blank Control
0 = Use BLANK* pin to indicate the active pixel region in slave mode.
1 = Use HBLANK, HACTIVE, VACTIVE, and VBLANK registers to determine the active pixel
region in slave mode.
PCLK_EDGE
FLDMODE
Pixel Clock Edge Sample Select
0 = P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK* data sampled at the rising edge of the system clock.
1 = P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK* data sampled at the falling edge of the system clock.
Field Tolerance
0 = A falling edge of VSYNC* that occurs within ±¼ of a scan line from the falling edge of
HSYNC* indicates the beginning of odd field. A falling edge of VSYNC* that occurs
within ± 1/4 scan line from the center of the line indicates the beginning of even field.
1 = A falling edge of VSYNC* that occurs during HSYNC* high indicates the beginning of
odd field. A falling edge of VSYNC* that occurs during HSYNC* low indicates the
beginning of even field.
D860DSA
Conexant
5-21
CONEXANT [ CONEXANT SYSTEMS, INC ]
