5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 18
Default
Value
Register
18
D7
D6
D5
D4
D3
D2
D1
D0
3F
YDELAY[2:1]
EN_DAC_F
EN_DAC_E
EN_DAC_D
EN_DAC_C
EN_DAC_B
EN_DAC_A
YDELAY[2:1]
MSBs of Luma Delay in Pixels for CVBS_DLY Outputs
YDELAY[0] is in 1/2 pixel increments, at 3C[6].
00 = No delay.
01 = Delay 1 pixel.
10 = Delay 2 pixels.
11 = Delay 3 pixels.
EN_DAC_F
EN_DAC_E
EN_DAC_D
EN_DAC_C
EN_DAC_B
EN_DAC_A
Enable DAC F
Enable DAC E
Enable DAC D
Enable DAC C
Enable DAC B
Enable DAC A
0 = Disable individual DAC output.
1 = Enable individual DAC output.
5-20
Conexant
D860DSA