5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 0B–0C
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
0B
0C
0C
HBLANK[7:0]
01
Reserved
HBLANK[9:8]
Reserved bits should be set to zero when written and will return zero when read.
HBLANK[9:0]
Horizontal Blanking Length
Determines the number of system clocks between 50% point of the leading edge of the
analog horizontal sync, as well as the relationship between the leading edge of the pulse on
the HSYNC* pin and active video. If HBLANK is even, the relationship between the register
and horizontal blanking in the encoded waveform is:
HBLANK = (desired horizontal blanking in system clocks) + 14
If HBLANK is odd, the relationship is:
HBLANK = (desired horizontal blanking in system clocks) + 15
Because, in either case you will get an even horizontal blanking in the encoded video
waveform, the only reason for having an odd HBLANK value is to align the active video
window with the encoding data stream. The relationship between HBLANK and the position
of active video on the P, OSD, and ALPHA pins is:
HBLANK = [(HSYNC* pin to active video) + 2 + HSYNC_OFF]
master mode
HBLANK = [(HSYNC* pin to active video) + 3] slave mode BLK_IGNORE bit = 1
Register 0D
Default
Register
D7
D6
D5
D4
D3
D2
D1
D0
Value
0D
13
VBLANK[7:0]
VBLANK[7:0]
Vertical Blanking Length
Line number of first active line (number of blank lines + 1),
measured from (0V) vertical sync(1)
.
Register 0E–0F
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
0E
0F
F1
00
VACTIVE[7:0]
Reserved
VACTIVE[8]
Reserved bits should be set to zero when written and will return zero when read.
VACTIVE[8:0] Number of Active Lines per Field
5-16
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
