5.0 Serial Programming Interface and Registers
5.3 Register Index
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-3. Register Index (5 of 5)
Default
Value(1)
Field
Register
Description
—
4C[7:0]
4B[7:0]
4A[3:0]
WSDAT[20:1]
WSS and CGMS Data Bits
—
80
80
4
01[1]
XDS_STAT
XDSB1[7:0]
XDSB2[7:0]
XDSSEL[3:0]
Extended Data Services Buffer Status
40[7:0]
41[7:0]
49[7:4]
First Byte of Extended Data Services Information
Second Byte of Extended Data Services Information
Line Position of Extended Data Services Content
7
1
73[7:4]
1C[0]
XL_GAIN[3:0]
XL_LOCK
Accelerated Locking Gain
Accelerated Locking
01
2
3C[5:4]
73[3:0]
3C[3]
XL_MDSEL[1:0]
XL_SAT[3:0]
XL_SATEN
XL_VRI
Accelerated Locking Mode Select
Accelerated Locking Saturation
0
Accelerated Locking Saturation Enable
Accelerated Locking Vertical Realignment Initiation
Luminance Level Offset (brightness control)
Luma Delay in 1/2 Pixel Increments for CVBS_DLY Outputs
1
1C[7]
00
000
37[7:0]
Y_OFF[7:0]
YDELAY[2:0]
18[7:6]
3C[6]
NOTE(S):
(1)
Default values in this table refer to hexadecimal values if the register field contains four or more bits; otherwise the value is
binary.
2. Internal timing and the values programmed into the registers reference the analog VSYNC pulse (O ) as line #1 (see
V
Figures 3-1 and 3-2).
3. System clock = F = 2x luminance sample frequency.
CLK
5-12
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
