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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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3.0 Registers  
Bt8370/8375/8376  
3.2 Global Control and Status Registers  
Fully Integrated T1/E1 Framer and Line Interface  
JAUTO  
Enable JCLK AccelerationWhen active, the jitter attenuated output clock (JCLK) phase is  
accelerated (added or subtracted) if the elastic store depth is within 1 Unit Interval (UI) of its  
limit. JCLK frequency is increased if the depth is within 1 UI of overflow, or decreased if the  
depth is within 1 UI of under-run. JAUTO does not affect JAT operation during other depth  
conditions. The amount of JCLK acceleration is proportional to the proximity of the elastic  
store limit, quantized in 0.125 UI steps. The JCLK phase is accelerated in 5 ns increments for  
each quantized step, to a total of 40 ns (maximum 0.08 UI output jitter). JAUTO expands the  
JAT loop bandwidth during near-limit conditions and allows JCLK to remain  
frequency-locked during an instantaneous reference clock switchover. Clock acceleration (±)  
is reported in CKERR interrupt [addr 006] and CPDERR [addr 021] status. JAUTO cannot  
prevent elastic store data errors [JERR; addr 006] if an invalid, out-of-frequency range clock is  
applied on the JAT reference input. If JCLK is programmed to free-run (JFREE), the processor  
must disable JAUTO. The processor can optionally disable JAUTO to prevent unnecessary  
clock acceleration when JCLK references CLADI, or during RLOS, RALOS, or TLOC error  
conditions.  
0 = no acceleration  
1 = enable JCLK acceleration  
JCENTER  
Force JAT to Center (not auto clear)Writing a 1 and then a 0 to JCENTER resets the elastic  
store write pointer and forces the elastic store read pointer to 1-half the programmed JSIZE.  
The processor writes JCENTER at power-up. Depending upon which JAT reference is  
selected, the processor can optionally assert JCENTER after recovery from a loss of signal  
(RLOS or RALOS) or in response to a transmit loss of clock (TLOC), or after recovering from  
a persistent clock error (CKERR).  
0 = normal operation  
1 = recenter JAT elastic store  
JSIZE[2:0]  
JAT Elastic Store SizeSelects the maximum depth of JAT elastic store. The 32-bit depth is  
sufficient to meet jitter attenuation requirements in all cases where JAT cutoff frequency is  
programmed at 6 Hz and the selected clock reference is frequency-locked. However, in cases  
where an external reference is selected or a narrow loop bandwidth is programmed, the elastic  
store depth can tolerate up to ±64 Unit Intervals (128 bits) of accumulated phase offset.  
JSIZE  
000  
Elastic Store Size  
8 Bits  
001  
16 Bits  
010  
32 Bits  
011  
64 Bits  
1xx  
128 Bits  
3-12  
Conexant  
N8370DSE  
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