Bt8370/8375/8376
3.0 Registers
Fully Integrated T1/E1 Framer and Line Interface
3.3 Interrupt Control Register
3.3 Interrupt Control Register
Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no
effect.
003—Interrupt Request Register (IRR)
An IRR bit is latched active (high) and the INTR* output pin is latched active (low) whenever an enabled
interrupt source reports an interrupt event in the corresponding Interrupt Status register [ISR7–ISR0; addr
004–00B]. IRR and INTR* are latched until the corresponding ISR register is read by the processor. Reading
ISR clears the respective IRR bit, independent of clearing ISR bits; therefore, persistently active ISR bits do not
assert INTR*. All IRR bits are logically OR'ed to activate INTR*, so the processor must read IRR = 00 before
exiting its interrupt service routine in order to confirm that the INTR* output has been de-asserted.
7
6
5
4
3
2
1
0
ALARM1
ALARM2
ERROR
COUNT
TIMER
DL1
DL2
PATT
ALARM1
Alarm 1 Interrupt Request—Indicates 1 or more receiver errors. The processor reads ISR7
[addr 004] to locate the specific source.
0 = no event
1 = active interrupt request
ALARM2
Alarm 2 Interrupt Request—Indicates 1-second timer expiration, or detection of 1 or more
transmitter errors or inband loopback codeword. The processor reads ISR6 [addr 005] to locate
the specific source.
0 = no event
1 = active interrupt request
ERROR
COUNT
TIMER
Error Interrupt—Indicates 1 or more errors detected by the receive framer, JAT, CLAD,
RSLIP, or TSLIP circuits. The processor reads ISR5 [addr 006] to locate the specific source.
0 = no event
1 = active interrupt request
Counter Overflow Interrupt—Indicates 1 or more error counts [addr 050–05A] have issued an
overflow interrupt. The processor reads ISR4 [addr 007] to locate the specific source.
0 = no event
1 = active interrupt request
Timer Interrupt Request—Indicates the transmit, receive, or system bus timebase has reached
a frame count terminus, or the receive signaling stack [STACK; addr 0DA] has been updated
with new signaling during the prior multiframe. The processor reads ISR3 [addr 008] to locate
the specific source.
0 = no event
1 = active interrupt request
DL1
Data Link Controller 1 or BOP Transmit—Indicates a transmit or receive interrupt issued by
DL1 or BOP transceiver has begun transmitting a priority codeword from TBOP [addr 0A1].
The processor reads ISR2 [addr 009] to locate the specific source.
0 = no event
1 = active interrupt request
N8370DSE
Conexant
3-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
