CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.2 Control Register Overview
Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers (2 of 2)
Address
0x16
Name
Function
HDR_VAL0_34
HDR_VAL1_12
HDR_VAL1_34
HDR_VAL2_12
HDR_VAL2_34
HDR_VAL3_12
HDR_VAL3_34
HDR_MSK0_12
HDR_MSK0_34
HDR_MSK1_12
HDR_MSK1_34
HDR_MSK2_12
HDR_MSK2_34
HDR_MSK3_12
HDR_MSK3_34
RX_IDLE_12
RX_IDLE_34
IDLE_MSK_12
IDLE_MSK_34
CONFIG_4
Receive Port 0 Header Value - Octets 3, 4
Receive Port 1 Header Value - Octets 1, 2
Receive Port 1 Header Value - Octets 3, 4
Receive Port 2 Header Value - Octets 1, 2
Receive Port 2 Header Value - Octets 3, 4
Receive Port 3 Header Value - Octets 1, 2
Receive Port 3 Header Value - Octets 3, 4
Receive Port 0 Header Mask - Octets 1, 2
Receive Port 0 Header Mask - Octets 3, 4
Receive Port 1 Header Mask - Octets 1, 2
Receive Port 1 Header Mask - Octets 3, 4
Receive Port 2 Header Mask - Octets 1, 2
Receive Port 2 Header Mask - Octets 3, 4
Receive Port 3 Header Mask - Octets 1, 2
Receive Port 3 Header Mask - Octets 3, 4
Receive Idle Header Value - Octets 1, 2
Receive Idle Header Value - Octets 3, 4
Receive Idle Header Mask - Octets 1, 2
Receive Idle Header Mask - Octets 3, 4
Configuration Control Register 4
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x60
IDLE_PAY
Transmit Idle Cell Payload Value
UTOPIA_1
Utopia Port Control Register 1
UTOPIA_2
Utopia Port Control Register 2
EN_LINE_INT
EN_EVENT_INT
EN_OVFL_INT
EN_CELL_INT
CONFIG_5
Line/PHY Status Interrupt Enable Register
Status Event Interrupt Enable Register
Counter Overflow Interrupt Enable Register
Cell Counter Interrupt Enable Register
Configuration Control Register 5
TX_K1K2
Transmit K1, K2 Value for SONET APS
Receive K1, K2 Value for SONET APS
HDLC Data Link Control and Status Register
RX_K1K2
DL_CTRL_STAT
100046C
Conexant
3-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
