CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.8 FEAC Channel and HDLC Data Link Programming
2.8.5 Receiver Response Example
The following example shows the sequence necessary to receive an 8-byte hex
message that was stored starting in the low half of the receive buffer. In this
example, the final interrupt indicates that two more bytes are present in the
buffer; however, these bytes are FCS bytes, not message bytes.
When an interrupt is received, the processor reads DL_CTRL_STAT [0x60] to
determine the source of the interrupt. If the source is determined to be the receive
HDLC data link, the processor responds in the following manner (the status
shown below ignores bits 15 and 14 in DL_CTRL_STAT):
at RX Interrupt:
read address 0x60 to get status (status = 18xx:
bytes = 3, idle = 0)
read address 0x58 to get 1st and 2nd data bytes
read address 0x59 to get 3rd and 4th data bytes at RX
Interrupt:
read address 0x60 to get status (status = 38xx:
bytes = 7, idle = 0)
read address 0x5A to get 5th and 6th data bytes
read address 0x5B to get 7th and 8th data bytes at RX
Interrupt:
read address 0x60 to get status(status = 0Cxx or 0Exx
bytes = 1, idle = 1, bad fcs = 0 or 1)
read address 0x58 if desired (FCS bytes 1 and 2)
100046C
Conexant
2-51
CONEXANT [ CONEXANT SYSTEMS, INC ]
