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28222-13 参数 Datasheet PDF下载

28222-13图片预览
型号: 28222-13
PDF下载: 下载PDF文件 查看货源
内容描述: ATM发射器/接收器与UTOPIA接口 [ATM Transmitter/Receiver with UTOPIA Interface]
分类和应用: 异步传输模式ATM
文件页数/大小: 161 页 / 1722 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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3.0 Registers  
CN8223  
3.2 Control Register Overview  
ATM Transmitter/Receiver with UTOPIA Interface  
3.2 Control Register Overview  
Table 3-2 lists the 52 control registers of the CN8223. Control registers are realized as latches within the  
CN8223 and are programmed by a write operation from the microprocessor. No initialization is provided for  
operational purposes. All registers must be initialized as required for each application by the microprocessor. A  
reset signal on the RESET pin (pin 118) resets counters and framer state machines. RESET does not affect  
control register contents.  
Control bits that do not have a defined function are reserved and must be written to 0. All control registers  
can be read to verify contents, except those control bits whose functions cause single events and are, therefore,  
not latched.  
Control registers in this section have been ordered by function: 7 control configurations, 19 control  
transmitter functions, 22 control receiver functions, and 4 enable interrupts.  
Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers (1 of 2)  
Address  
0x00  
Name  
Function  
Configuration Control Register 1  
CONFIG_1  
CONFIG_2  
CONFIG_3  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
0x07  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
0x10  
0x11  
0x12  
0x13  
0x14  
0x15  
Configuration Control Register 2  
Configuration Control Register 3  
TXFEAC_ERRPAT  
CELL_GEN_0  
CELL_GEN_1  
CELL_GEN_2  
CELL_GEN_3  
TX_RATE_23  
TX_RATE_01  
TX_IDLE_12  
TX_IDLE_34  
TX_HDR0_12  
TX_HDR0_34  
TX_HDR1_12  
TX_HDR1_34  
TX_HDR2_12  
TX_HDR2_34  
TX_HDR3_12  
TX_HDR3_34  
CELL_VAL  
Transmit FEAC/BIP-8 Error Pattern  
Cell Generation Control - Port 0  
Cell Generation Control - Port 1  
Cell Generation Control - Port 2  
Cell Generation Control - Port 3  
Transmit Rate Control Value - Ports 2, 3  
Transmit Rate Control Value - Ports 0, 1  
Transmit Idle Header Value - Octets 1, 2  
Transmit Idle Header Value - Octets 3, 4  
Transmit Port 0 Header Value - Octets 1, 2  
Transmit Port 0 Header Value - Octets 3, 4  
Transmit Port 1 Header Value - Octets 1, 2  
Transmit Port 1 Header Value - Octets 3, 4  
Transmit Port 2 Header Value - Octets 1, 2  
Transmit Port 2 Header Value - Octets 3, 4  
Transmit Port 3 Header Value - Octets 1, 2  
Transmit Port 3 Header Value - Octets 3, 4  
Cell Validation Control  
HDR_VAL0_12  
Receive Port 0 Header Value - Octets 1, 2  
3-2  
Conexant  
100046C