3.0 Registers
CN8223
3.3 Configuration Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
Table 3-3. Valid Combinations of CONFIG_1, Bits 0–7
Disable
B3ZS/
HDB3
Enable
Parallel
Interface
Enable
HEC
Align
PHY
Type of Line Input Signal
Type
Unframed
Input
External
Framer
DS1
0
0
1
1
2
2
2
3
3
3
0
1
0
1
0
0
1
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0 or 1
DS1 (externally gapped 192 bits/frame)
E1
0
0
0
0 or 1
E1 (externally gapped TS0 and TS16)
DS3, Internal Framer
0
0
0 or 1
0 or 1
DS3, External Framer
0
0 or 1
DS3, External Framer (gapped 84/85 bits)
E3, Internal G.751 Format
E3, External G.751 Format
0
0 or 1
0
0
0
0
0
E3, External G.751 Format
(gapped 1st 16 bits)
0
E3, Internal G.832 Format
4
5
6
7
0
x
x
x
x
x
0 or 1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
E4, Internal G.832 Format
1
0 or 1
1
STS-1, Internal Framer
STS-3c/STM-1, Internal Framer
Parallel or TAXI Interface, 53 Octet Cells
Notes: 1. “x” = Don’t Care
0
3-6
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
