4-Level FSK Modem Data Pump
Page 29 of 50
MX929B PRELIMINARY INFORMATION
4.5.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB, RSID, or R4S task is
written to the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the
Command Register or by changing the TX /
RX or PSAVE bits of the Mode Register.
In transmit mode this bit is '0'.
4.5.5.5 Status Register B3: CRCERR - CRC Checksum Error
In receive mode, this bit will be updated at the end of a SFP, RHB, RILB, or RSID task to reflect the result of
the receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error.
Note: This bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task or by changing the TX /RX , or PSAVE bits of the Mode Register. In
transmit mode this bit is '0'.
4.5.5.6 Status Register B2: 'S' Symbol Ready
In receive mode, this bit is set to '1' whenever an 'S' symbol has been received. The PC may then read the
value of the symbol from the SVAL field of the Status Register. In transmit mode, this bit is set to '1' whenever
an 'S' symbol has been transmitted.
The bit is cleared to '0' immediately after a read of the Status Register, by a RESET task or by changing the
TX /RX or PSAVE bits of the Mode Register.
4.5.5.7 Status Register B1, B0: SVAL - Received 'S' Symbol Value
In receive mode, these two bits reflect the value of the latest received 'S' symbol. In transmit mode, these two
bits
will be '0'.
4.5.6 Data Quality Register
In receive mode, the MX929B continually measures the 'quality' of the received signal, by comparing the
actual received waveform over the previous 64 symbol times against an internally generated 'ideal' 4-level
FSK baseband signal.
The result is placed into bits 3-7 of the Data Quality Register for the µC to read at any time, bits 0-2 being
always set to '0'. Figure 15 shows how the value (0-255) read from the Data Quality Register varies with
received signal-to-noise ratio:
250
200
150
DQ
100
50
0
8
9
10
11
12
13
14
15
16
S/N dB (Noise in 2 x Symbol Rate Bandwidth)
Figure 15: Typical Data Quality Reading vs S/N
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