GMSK Packet Data Modem and RF Transceiver
CMX990
5.2
µC Interface
5.2.1 Memory Map and Interface
The following is a summary of the internal registers as seen by the host, details of operation may be
found in the relevant section.
Address
$00
$01
$02
$03
$04
$05
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$20
$21
$22
$23
$24
$25
$26
$27
$28
$TBA
Read
Write
Data Buffer (Rx)
Data Buffer (Tx)
Command
Status 1
Data Quality
Control
Status 2
Mode
Freq Offset
Power Up 1
RSSI
Power Up 2
Aux ADC 0 LSB
Aux DAC 0 LSB
Aux DAC 0 MSB
Aux DAC 1 LSB
Aux DAC 1 MSB
Aux DAC 2 LSB
Aux DAC 2 MSB
Aux DAC 3 LSB
Aux DAC 3 MSB
RAM DAC control
Aux ADC control 1
Aux ADC control 2
-
Aux ADC 0 MSB
Aux ADC 1 LSB
Aux ADC 1 MSB
Aux ADC 2 LSB
Aux ADC 2 MSB
Aux ADC 3 LSB
Aux ADC 3 MSB
Aux ADC 4 LSB
Aux ADC 4 MSB
Aux ADC 5 LSB
Aux ADC 5 MSB
-
Aux Ram Data1 LSB
Aux Ram Data1 MSB
Aux Ram Data2 LSB
Aux Ram Data2 MSB
Analogue Setup 1
Analogue Setup 2
Special Command
Special Data0 LSB
Special Data0 MSB
Special Data1 LSB
Special Data1 MSB
Main PLL M div LSB
Main PLL M div MSB
Main PLL N div LSB
Main PLL N div NSB
Main PLL N div MSB
Aux PLL M div LSB
Aux PLL M div MSB
Aux PLL N div LSB
Aux PLL N div MSB
Clock Control
-
-
-
Analogue Setup 1
Analogue Setup 2
-
Special Data0 LSB
Special Data0 MSB
Special Data1 LSB
Special Data1 MSB
-
-
-
-
-
-
-
-
-
Note: All unused addresses from $00 to $3F are reserved for future use.
ã 2004 CML Microsystems Plc
44
D/990/1
CMLMICRO [ CML MICROCIRCUITS ]
