GMSK Packet Data Modem and RF Transceiver
CMX990
5.1.6.2 Receive Frame Example
If the device is required to decode a Mobitex Frame the following control signals should be
issued to the modem. The host should set the Control Register and activate the Acquire I Q
Offset and Acquire AFC each time a new channel is selected when the RSSI indicates a valid
signal or carrier only is present before packets are decoded. This also assumes that the device
is initially not in powersave, the SCREN is set as required, TXRXN bit is set to ‘0’ and a Packet
Detect event has occurred, or a Frame Head is imminently expected:
1. 2 Frame Sync bytes are loaded.
2. 2 bits after the carrier has been detected, a LFSB task is loaded, along with setting the
Acquire Bit Clock to initiate the bit clock extraction sequence.
3. Device interrupts host µC with IRQN when 2nd byte is read from Data Buffer.
4. Status Register is read, 12 bits later task is set to SFH to search for a Mobitex Frame
Head.
5. Device will interrupt host µC with IRQN when valid Frame Sync is detected and header
bytes decoded.
6. Host µC reads Status 1 Register, checks MOBAN and CRCFEC bit and reads out 2 Frame
Head control bytes.
7. Host µC disables Packet Detect and sets the task to RDB to receive a Mobitex Data Block.
8. Device will interrupt host µC with IRQN when the Data Block has been received and the
CRC has been calculated.
9. Host µC reads Status 1 Register, checks CRC validity and reads 18 Data Block bytes. The
Data Quality Register can also be read to obtain the received S/N level.
10. Host µC sets task if more information is expected:
GOTO ‘4’ if last Data Block and another Frame Head imminently expected.
GOTO ‘7’ if another Mobitex Data Block expected.
If the last Data Block has been decoded and no more information is expected then the task bits
need not be set as the device will automatically select the idle state.
A top level flowchart of the receive process is shown in Figure 20.
ã 2004 CML Microsystems Plc
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D/990/1
CMLMICRO [ CML MICROCIRCUITS ]
