GMSK Packet Data Modem and RF Transceiver
CMX990
5.1.4.5 Status 1 Register
This register may be read by the µC to determine the current state of the modem.
Status 1 Register
$01
Read
7
6
5
4
3
2
1
0
Bit:
Packet
Detect
IRQ
BFREE
IBEMPTY
DIBOVF
CRCFEC
DQRDY
MoBaN
Status 1 Register, B7: IRQ - Interrupt Request
This bit is set to ‘1’ by:
The Status 1 Register BFREE bit going from ‘0’ to ‘1’, unless this is caused by a
RESET task or by a change to the Mode Register Enable Baseband or TXRXN
bits.
or
The Status 1 Register IBEMPTY bit going from ‘0’ to ‘1’, unless this is caused by
a RESET task or by changing the Mode Register Enable Baseband or TXRXN
bits.
or
or
or
The Status 1 Register DQRDY bit going from ‘0’ to ‘1’ (If DQEN = ‘1' ).
The Status 1 Register DIBOVF bit going from ‘0’ to ‘1’.
The Status 1 Register Packet Detect bit going from ‘0’ to ‘1’ if the Enable Packet
Detect bit is set in the Command Register.
or
The Status 2 Register bits 7, 3, 2, 1 or 0 going from ‘0’ to ‘1’.
The host must read Status 1 Register first after detecting or looking for an interrupt condition.
The IRQ bit is cleared to ‘0’ immediately after a read of the Status Register that caused the
interrupt. In the case where 1 or more bits in Status 2 Register cause an interrupt the IRQ bit is
only cleared after reading Status 2 Register.
If the IRQEN bit of the Mode Register is ‘1’, then the chip IRQN output will be pulled low (to
Vss) whenever the IRQ bit is ‘1’.
Status 1 Register, B6: BFREE - Data Buffer Free
This bit reflects the availability of the Data Buffer and is cleared to ‘0’ whenever a task other
than NULL, RESET or TSO is written to the Command Register.
In transmit mode, the BFREE bit will be set to ‘1’ (also setting the Status 1 Register IRQ bit to
‘1’) when the modem is ready for the µC to write new data to the Data Buffer and the next task
to the Command Register.
In receive mode, the BFREE bit is set to ‘1’ (also setting the Status 1 Register IRQ bit to ‘1’) by
the modem when it has completed a task and any data associated with that task has been
placed into the Data Buffer. The µC may then read that data and write the next task to the
Command Register.
The BFREE bit is also set to ‘1’, but without setting the IRQ bit, by a RESET task or when the
Mode Register Enable Baseband or TXRXN bits are changed.
Status 1 Register, B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to ‘1’, also setting the IRQ bit, when less than two bits
remain in the Interleave Buffer. Any transmit task written to the modem after this bit goes to ‘1’
will be too late to avoid a gap in the transmit output signal.
The bit is also set to ‘1’ by a RESET task or by a change of the Mode Register TXRXN or
Enable Baseband bits, but in these cases the IRQ bit will not be set.
ã 2004 CML Microsystems Plc
34
D/990/1
CMLMICRO [ CML MICROCIRCUITS ]
