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CMX909B 参数 Datasheet PDF下载

CMX909B图片预览
型号: CMX909B
PDF下载: 下载PDF文件 查看货源
内容描述: GMSK分组数据调制解调器 [GMSK Packet Data Modem]
分类和应用: 调制解调器
文件页数/大小: 50 页 / 1302 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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GMSK Packet Data Modem  
CMX909B  
1.5.4.4 Mode Register  
The contents of this 8-bit write only register control the basic operating modes of the modem:  
Mode Register B7: IRQNEN - IRQN Output Enable  
When this bit is set to ‘1’, the IRQN chip output pin is pulled low (to V ) whenever the IRQ bit of  
ss  
the Status Register is a ‘1’.  
Mode Register B6: INVBIT - Invert Bits  
This bit controls inversion of transmitted and received bit voltages. When set to ‘1’ all data is  
inverted in the Tx and Rx data paths so a transmitted '1' is a voltage below V  
at the TXOP pin  
BIAS  
and a received '0' is a voltage above V  
this bit is set to ‘1’.  
at the RXIN pin. Data will be inverted immediately after  
BIAS  
Mode Register B5: TXRXN - Tx/Rx Mode  
Setting this bit to ‘1’ puts the modem into Transmit mode, clearing it to ‘0’ puts the modem into  
Receive mode. When changing from Rx to Tx there must be a 2-bit pause before setting a new  
task to allow the filter to stabilise. (See also PSAVE bit).  
Note that changing between receive and transmit modes will cancel any current task  
Mode Register B4: SCREN - Scramble Enable  
The scrambler only takes effect during the transmission or reception of a Mobitex Data Block, Short  
Data Block and during a TSO task. Setting this bit to ‘1’ enables scrambling, clearing it to ‘0’  
disables scrambling.  
The scrambler is only operative, if enabled by this control bit, during TSO, RDB, RSD, TSD or TDB,  
it is held in a reset state at all other times.  
This bit should not be changed while the modem is decoding or transmitting a Mobitex Data Block.  
Mode Register B3: PSAVE - Powersave  
When this bit is a ‘1’, the modem will be in a ‘powersave’ mode in which the internal filters, the Rx bit  
and Clock extraction circuits and the Tx o/p buffer will be disabled, and the TXOP pin will be  
connected to V  
through a high value resistance. If the PSBias or PSBiXt bit patterns are set in  
BIAS  
the Command Register, the V  
and Xtal/Clock circuits will be powersaved in accordance with the  
BIAS  
description in section 1.5.4.2. Setting the PSAVE bit to ‘0’ restores power to all of the chip circuitry.  
Note that the internal filters will take about 2 bit times to settle after the PSAVE bit is taken from ‘1’ to  
‘0’.  
ã 2001 Consumer Microcircuits Limited  
28  
D/909B/1  
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