GMSK Packet Data Modem
CMX909B
These bits control a frequency divider driven from the clock signal present at the XTALN pin, and
hence determine the nominal bit rate. The table below shows how bit rates of 4000 to 38400
bits/sec may be obtained from common Xtal frequencies:
B5
Xtal/Clock Frequency (MHz)
8.192
9.8304
4.9152
4.096
(12.288/3)
2.048
4.9152
2.048
(6.144/3)
1.024
2.4576
(12.288/5)
1.2288
1
4.096
2.4576
0
(12.288/3)
(6.144/3)
(12.288/5)
Division Ratio:
XtalFrequency
Data Rate
B7 B6
Data Rate (bits per second)
0
0
1
1
0
1
0
1
256
512
1024
2048
128
256
512
32000
16000
8000
38400
19200
9600
16000
8000
4000
19200
9600
4800
8000
4000
9600
4800
1024
4000
4800
Note: Device operation is not guaranteed below 4000 or above 38400 bits/sec.
The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide;
C3 = C4 = 33pF for X1 < 5MHz, and C3 = C4 = 18pF for X1 > 5MHz.
Control Register B4: DARA - Data Rate and Mode Register B0 - HIBW
These bits operate in both transmit and receive modes, optimising the modem's internal signal
filtering according to the relevant bit rate.
Control Register:
Mode Register:
Data Rate
(bits/sec)
<10k
Reserved
10k – 20k
>20k
B4 (DARA)
B0 (HIBW)
0
0
1
1
0
1
0
1
ã 2001 Consumer Microcircuits Limited
26
D/909B/1
CMLMICRO [ CML MICROCIRCUITS ]
