GMSK Packet Data Modem
CMX909B
Figure 10 Receive Mode Timing Diagram
Task
Typical time
(bit-times)
t3
t6
t7
Time to receive all bits of task
SFH
R3H
RDB
RSB
RSD
56
24
240
8
72
14
18
218
6
Maximum time between first bit of task
entering de-interleave circuit and task
being written to modem
SFH
R3H
RDB
RSB
RSD
Any
64
1
Time from last bit of task entering de-interleave
circuit to BFREE going to a logic ‘1’ (high)
ã 2001 Consumer Microcircuits Limited
24
D/909B/1