GMSK Packet Data Modem
CMX909B
Status Register B2: DQRDY - Data Quality Reading Ready
In receive mode, this bit is set to ‘1’ whenever a Data Quality reading has been completed. See
section 1.5.4.6.
The bit is cleared to '0' by a read of the Data Quality Register.
Immediately after a RESET task, or a change in the PSAVE or TXRXN bits to ‘0’, the DQRDY bit
may be set and generate an interrupt. The value in the Data Quality Register will not be valid in this
case.
Status Register B1: MOBAN - Mobile or Base Bit Sync Received
In receive mode this bit is updated at the end of the SFS and SFH tasks. This bit is set to ‘1’
whenever the 3 bits immediately preceding a detected Frame sync are ‘011’ (received left to right),
with up to any one bit in error. The bit is set to ‘0’ if the bit pattern is ‘100’, again with up to any one
bit in error. Thus, if this bit is set to ‘1’ then the received message is likely to have originated from a
Mobile and if it is set to ‘0’ from a Base Station. See section 1.5.3.
In transmit mode this bit is a logic ‘0’.
Status Register B0: EOP/ENV - End of Packet/Envelope Detect
This bit indicates the status of the End of Packet and Envelope detector circuits as indicated in the
description of Command Register bits B5 and B4.
In transmit mode this bit will be ‘0’.
1.5.4.6 Data Quality Register
This is intended to indicate the quality of the receive signal during a Mobitex Data Block or 30 single
bytes. In receive mode, the modem measures the ‘quality’ of the received signal by comparing the
actual received zero crossing time against an internally generated time. This value is averaged
over 240 bits and at the end of the measurement the Data Quality Register and the DQRDY bit in
the Status Register is updated. Note: An interrupt will only occur at this time if the DQEN bit = ‘1’.
To provide synchronisation with Data Blocks, and hence ensure the Data Quality Register is
updated in preparation to be read when the RDB task finishes, the measurement process is reset at
the end of tasks SFH, SFS, RDB and R3H.
The least significant 2 bits (B0 and B1) will be set to the output of the Envelope and End of Packet
detector circuits respectively if either of the ENV or EOP bits have been set in the Command
Register. After a RESET or if the transmit or power save modes have been set these bits will
indicate the least significant bits of the quality reading. The state of the ENV and EOP bits have no
other effect on the operation of the Data Quality Register.
In transmit mode all bits of the Data Quality Register will be ‘0’.
Figure 12 shows how the value (0-240) read from the Data Quality Register varies with received
signal to noise ratio.
ã 2001 Consumer Microcircuits Limited
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D/909B/1
CMLMICRO [ CML MICROCIRCUITS ]
