GMSK Packet Data Modem
CMX909B
Status Register B6: BFREE - Data Buffer Free
This bit reflects the availability of the Data Buffer and is cleared to ‘0’ whenever a task other than
NULL, RESET or TSO is written to the Command Register.
In transmit mode, the BFREE bit will be set to ‘1’ (also setting the Status Register IRQ bit to ‘1’) by
the modem when the modem is ready for the µC to write new data to the Data Buffer and the next
task to the Command Register.
In receive mode, the BFREE bit is set to ‘1’ (also setting the Status Register IRQ bit to ‘1’) by the
modem when it has completed a task and any data associated with that task has been placed into
the Data Buffer. The µC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to ‘1’, but without setting the IRQ bit, by a RESET task or when the Mode
Register PSAVE or TXRXN bits are changed.
Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to ‘1’, also setting the IRQ bit, when less than two bits remain in
the Interleave Buffer. Any transmit task written to the modem after this bit goes to ‘1’ will be too late
to avoid a gap in the transmit output signal.
The bit is also set to ‘1’ by a RESET task or by a change of the Mode Register TXRXN or PSAVE
bits, but in these cases the IRQ bit will not be set.
The bit is cleared to ‘0’ by writing a task other than NULL, RESET or TSO to the Command
Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level voltage
(V ) will be applied to the Tx low pass filter.
BIAS
In receive mode this bit will be ‘0’.
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to ‘1’ (also setting the IRQ bit) when a task is written to the
Command Register too late to allow continuous reception.
The bit is cleared to ‘0’ by reading the Status Register or by writing a RESET task to the Command
Register or by changing the PSAVE or TXRXN bits of the Mode Register.
In transmit mode this bit will be ‘0’.
Status Register B3: CRCFEC - CRC or FEC Error
In receive mode this bit will be updated at the end of a Mobitex Data Block task, after checking the
CRC, and at the end of receiving Frame Head control bytes, after checking the FEC. A ‘0’ indicates
that the CRC was received correctly or the FEC did not find uncorrectable errors, a ‘1’ indicates that
errors are present.
The bit is cleared to ‘0’ by a RESET task or by changing the PSAVE or TXRXN bits of the Mode
Register.
In transmit mode this bit will be ‘0’.
ã 2001 Consumer Microcircuits Limited
30
D/909B/1
CMLMICRO [ CML MICROCIRCUITS ]
