GMSK Packet Data Modem
CMX909B
Mode Register B2: DQEN - Data Quality IRQ Enable
In receive mode, setting this bit to ‘1’ causes the IRQ bit of the Status Register to be set to ‘1’
whenever a new Data Quality reading is ready. (The DQRDY bit of the Status Register will also be
set to ‘1’ at the same time.)
In transmit mode this bit has no effect.
Mode Register B1: HIXTL - High Xtal Drive
This bit controls the gain of the on chip Xtal driver. For 3V operation and crystals >5MHz it should
be set to ‘1’. At 5V, or whenever using crystals <5MHz, it should be set to ‘0’.
Mode Register B0: HIBW - High Filter Bandwidth
This bit controls the internal filtering of the device. See Control Register B4 for the setting of this bit.
1.5.4.5 Status Register
This register may be read by the µC to determine the current state of the modem.
Status Register B7: IRQ - Interrupt Request
This bit is set to ‘1’ by:
The Status Register BFREE bit going from ‘0’ to ‘1’, unless this is caused by a RESET
task or by a change to the Mode Register PSAVE or TXRXN bits.
or
The Status Register IBEMPTY bit going from ‘0’ to ‘1’, unless this is caused by a
RESET task or by changing the Mode Register PSAVE or TXRXN bits.
or
or
or
The Status Register DQRDY bit going from ‘0’ to ‘1’ (If DQEN = ‘1' ).
The Status Register DIBOVF bit going from ‘0’ to ‘1’.
The Status Register EOP/ENV bit going from ‘0’ to ‘1’ if ENV or EOP bits (not both)
are set in the Command Register.
or
The Status Register EOP/ENV bit going from ‘0’ to ‘1’ or ‘1’ to ‘0’ if both ENV and EOP
bits are set in the Command Register.
The IRQ bit is cleared to ‘0’ immediately after a read of the Status Register.
If the IRQEN bit of the Mode Register is ‘1’, then the chip IRQN output will be pulled low (to Vss)
whenever the IRQ bit is ‘1’.
ã 2001 Consumer Microcircuits Limited
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D/909B/1
CMLMICRO [ CML MICROCIRCUITS ]
