Marine VHF Audio and Signalling Processor
CMX885
48-pin
L4/Q3
30
Pin
Name
ADC4
Type
IP
Auxiliary ADC input (4)
Description
31
AVDD
PWR
Positive 3.3V supply rail for the analogue on-chip circuits.
Levels and thresholds within the device are proportional to
this voltage. This pin should be decoupled to AV
SS
by
capacitors mounted close to the device pins.
Auxiliary DAC output 1/RAMDAC
Auxiliary DAC output 2
Analogue Ground
Auxiliary DAC output 3
Auxiliary DAC output 4
Digital Ground
Internally generated 2.5V supply voltage. Must be decoupled
to DV
SS
by capacitors mounted close to the device pins. No
other connections allowed.
Input to the oscillator inverter from the Xtal circuit or external
clock source.
The output of the on-chip Xtal oscillator inverter
The 3.3V positive supply rail for the digital on-chip circuits.
This pin should be decoupled to DVss by capacitors mounted
close to the device pins
C-BUS: Serial data input from the µC
C-BUS: A 3-state C-BUS serial data output to the µC. This
output is high impedance when not sending data to the µC.
Reserved – do not connect this pin
Digital Ground
C-BUS: The C-BUS serial clock input from the µC
Synthesised Digital System Clock Output 2
C-BUS: The C-BUS chip select input from the µC - there is
no internal pullup on this input
On this device, the central metal pad (which is exposed on
Q3 packages only) may be electrically unconnected or,
alternatively, may be connected to Analogue Ground (AVss).
No other electrical connections are permitted.
32
33
34
35
36
37
38
DAC1
DAC2
AVSS
DAC3
DAC4
DVSS
VDEC
OP
OP
PWR
OP
OP
PWR
PWR
39
40
41
42
43
44
45
46
47
48
XTAL/CLK
XTALN
DVDD
CDATA
RDATA
-
DVSS
SCLK
SYSCLK2
CSN
IP
OP
PWR
IP
TS OP
NC
PWR
IP
OP
IP
E
XPOSED
M
ETAL
P
AD
SUBSTRATE
~
Notes:
IP
OP
BI
TS OP
PWR
NC
=
=
=
=
=
=
Input (+ PU/PD = internal pullup/pulldown resistor)
Output
Bidirectional
3-state Output
Power Connection
No Connection - should NOT be connected to any signal
©
2010 CML Microsystems Plc
8
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
