Marine VHF Audio and Signalling Processor
CMX885
8.2.2 Program Block 1 – Inband Tone Setup
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
P1.0
1
1
0
1
Audio Band Tones/Data Tx Level
Default values:
P1.0:
$800
$C8 (P1.0)
Audio Band Tones Tx Level
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
P1.0
1
1
0
1
Audio Band Tones/Data Tx Level
Bits 11 (MSB) to 1 (LSB) set the transmitted DTMF, Audio Tone and FSK signal level (pk-pk) with a
resolution of AVDD/2048 per LSB (1.611mV per LSB at AVDD=3.3V). Valid range for this value is 0 to
1536 – use with care as higher values may result in signal “clipping”.
Bit 0 reserved
8.2.3 Program Block 2 – reserved
8.2.4 Program Block 3 – AuxDAC, RAMDAC and Clock Control
This block is divided into two sub-blocks to facilitate loading the RAMDAC buffer. Set bit 15 to restart a
loading sequence. If bit 10 is set then loading the first ten locations will be skipped. If bit 10 is clear, the
first ten locations must be loaded before continuing to the RAMDAC load.
The internal clock dividers only require modification if a non-standard XTAL frequency is used (see Table
2).
Bit:
15
1
14
1
13
1
12
1
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
P3.0
AuxADC1 Average Counter
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.xx
P3.74
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
reserved
GP Timer value in Idle mode
VCO output and AUX clk divide in Idle mode
Ref clk divide in Rx or Tx mode
PLL clk divide in Rx or Tx mode
VCO output and AUX clk divide in Rx or Tx mode
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
Internal ADC/DAC clk divide in Rx or Tx mode
ADC Internal Control 1
ADC Internal Control 2
0
0
0
0
ADC Internal Control 3
User Defined RAMDAC Data 0
User Defined RAMDAC Data xx
User Defined RAMDAC Data 63
Default Values:
P3.0
P3.1
$000
$000
P3.2 - P3.7:
P3.8
see Table 2
$000
P3.9
$101
P3.10
$002
P3.11 - P3.74:
see Table 7
© 2010 CML Microsystems Plc
53
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
