Marine VHF Audio and Signalling Processor
CMX885
8.2
Programming Register Operation
In order to support radio systems that may not comply with the default settings of the CMX885, a set of
Program Blocks is available to customise the features of the device. It is envisaged that these blocks will
usually only be written to following a power-on of the device and hence can only be accessed while the
device is in Idle mode. Access to these blocks is via the Programming register ($C8).
All other interrupt sources should be disabled and the AuxADCs switched off while loading the Program
Blocks.
The Programming register should only be written to when the PRG flag in the Status register $C8:b0 is
set to 1 and the Rx and Tx modes are disabled (bits 0 and 1 of the Mode Control register both 0) and the
AuxADC is disabled.
The PRG flag is cleared when the Programming register is written to by the host. When the corresponding
programming action has been completed (normally within the C-BUS latency period, 250µs) the CMX885
will set the flag back to 1 to indicate that it is now safe to write the next programming value. The
Programming register must not be written to while the PRG flag bit is 0. Programming is performed by
writing a sequence of 16-bit words to the Programming register in the order shown in the following tables.
Writing data to the Programming register MUST be performed in the order shown for each of the blocks,
however the order in which the blocks are written is not critical. If later words in a block do not require
updating the user may stop programming that block when the last change has been performed. e.g. If
only 'Fine output Atten 1' needs to be changed the host will need to write to P4.0, P4.1 and P4.2 only.
The user must not exceed the defined word counts for each block.
The internal pointer for each Program block write is initialised by setting bit 15 to 1. Bits 14-12 are then
used to select the particular Program block in use as shown in Table 6. Subsequent writes to the Program
Register (with b15 cleared to 0) will increment the pointer until the end of the Program Block is reached.
Program Block 3 has an additional feature to facilitate RAMDAC programming, where the first eleven
entries of the block may be skipped by setting both b15 and b10 to 1 to initialise the pointer directly to the
start of the RAMDAC table.
Table 6 Program Block Selection
b15
1
1
1
1
b14
0
1
1
1
b13
x
0
0
1
b12
x
0
1
0
Bit Field (max)
Select Block 4
Select Block 0
Select Block 1
Select Block 2
Select Block 3
14
12
12
12
12
1
1
1
1
Once the final write to the Programming register has been executed, a final check of the PRG flag should
be performed before returning to normal operation.
© 2010 CML Microsystems Plc
51
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
