Marine VHF Audio and Signalling Processor
CMX885
0
8.2.1 Program Block 0 – Modem Configuration
Bit:
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
15
1
0
0
0
0
0
0
0
0
0
14
1
1
1
1
1
1
1
1
1
1
13
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
Pre
0
DSC Frame SynC
DSC Frame SynC
DSC Frame SynD
DSC Frame SynD
reserved
LSB
MSB
LSB
MSB
0
0
0
0
0
0
0
0
0
reserved
reserved
reserved
DSC Bit Sync
DSC Bit Sync
LSB
MSB
Default values:
P0.0
P0.1
P0.2
P0.3
P0.4
$23
P0.5
P0.6
P0.7
P0.8
P0.9
$00
$00
$00
$55
$55
$CB
$33
$B4
$00
This initiates the device with the DSC frame sync pattern of $CB23 and bit sync of alternate 1s and 0s.
$C8 (P0.0-3) DSC Frame Sync
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
P0.0
1
1
0
0
Pre
0
DSC Frame SynC LSB
DSC Frame SynC MSB
DSC Frame SynD LSB
DSC Frame SynD MSB
P0.1
P0.2
P0.3
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
Bits 7 to 0 set the Frame Sync pattern used in Tx and Rx DSC data. Bit 7 of the MSB is compared to the
earliest received data. Note that SynT is the inverse pattern of SynC.
Bit 11 enables pre-emphasis on DSC transmission.
$C8 (P0.4-7) reserved
$C8 (P0.8-9) DSC Bit Sync
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
P0.8
0
1
0
0
0
0
DSC Bit Sync LSB
DSC Bit Sync MSB
P0.9
0
1
0
0
This bit pattern is used when transmitting the bit sync.
© 2010 CML Microsystems Plc
52
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
