Marine VHF Audio and Signalling Processor
CMX885
0
$C8 (P4.0)
Fine Input Gain 1 and Fine Input Gain 2
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P4.0
1
0
Fine Input Gain 1 (unsigned integer)
Fine Input Gain 2 (unsigned integer)
P4.1
0
0
Gain = 20 × log([32768-IG]/32768)dB. IG is the unsigned integer value in the ‘Fine Input Gain’ field.
Fine input gain adjustment should be kept within the range 0 to -3.5dB. This adjustment occurs after the
coarse input gain adjustment (register $B1)
$C8 (P4.2-3) Fine Output Gain 1 and Fine Output Gain 2
Bit:
P4.2
P4.3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
Fine Output Gain 1 (unsigned integer)
Fine Output Gain 2 (unsigned integer)
0
0
Gain = 20 × log([32768-OG]/32768)dB. OG is the unsigned integer value in the ‘Fine Output Gain’ field.
Fine output gain adjustment should be kept within the range 0dB to -3.5dB. This adjustment occurs
before the coarse output gain adjustment (register $B0). Alteration of Fine Output Gain 1 will affect the
gain of both MOD1 and AUDIO outputs.
$C8 (P4.4-5) Output 1 Offset and Output 2 Offset
Bit:
P4.4
P4.5
15
14
13
12
11
10
9
8
7
6
5
4
DD
DD
3
2
1
0
0
0
2’s complement Offset for MOD1, resolution = AV
2’s complement Offset for MOD2, resolution = AV
/ 65536 per LSB
/ 65536 per LSB
0
0
The programmed value is subtracted from the output signal. Can be used to compensate for inherent
offsets in the output path via MOD1 (Output 1 Offset) and MOD2 (Output 2 Offset). It is recommended
that the offset correction is kept within the range +/-50mV. This adjustment occurs before the coarse
output gain adjustment (register $B0), therefore an alteration to the latter register will require a
compensation to be made to the output offsets.
$C8 (P4.6)
Ramp Rate Control
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P4.6
0
0
Ramp Rate Up Control (RRU)
Ramp Rate Down Control (RRD)
The ramp-up and ramp-down rates can be independently programmed. The ramp rates apply to all the
analogue output ports. They only affect those ports being turned on (ramp-up) or turned off (ramp down).
The ramp rates should be programmed before ramping any outputs.
Time to ramp-up to full gain =
Time to ramp down to zero gain =
(1 + RRU) × 1.333ms
(1 + RRD) × 1.333ms
Ramp up starts from when the transmit mode starts (Mode Control Register $C1:b1 set to 1). Ramp
down starts from when transmit mode is turned off (Mode Control Register $C1:b1 cleared to 0).
$C8 (P4.7)
Transmit Limiter Control
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P4.7
0
0
Limiter Setting
This unsigned number sets the clipping point (maximum deviation from the centre value) for the MOD1
and MOD2 pins. The maximum setting ($3FFF) is VBIAS ± (AV /2) i.e. output limited from 0 to AV
.
DD
DD
of 3.3V, the resolution is approx. 0.3mV per LSB.
For an AV
DD
© 2010 CML Microsystems Plc
55
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
