Marine VHF Audio and Signalling Processor
CMX885
8.1.4 AuxDAC Control/Data – $A8 write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RAM
DAC
ENA
0
0
DAC Sel
Aux DAC Data/RAMDAC Control
b15 enable selected Aux DAC
b14 reserved
0 = disable
1 = enable
b13 reserved
b12 RAMDAC enable
0 = AuxDAC1 operates normally
1 = AuxDAC1 operates as a RAMDAC4. Data in b0-6 controls the
RAMDAC functions.
b11-b10 Select the AuxDAC that b9-b0 data will be written to
00 = AuxDAC1
01 = AuxDAC2
10 = AuxDAC3
11 = AuxDAC4
b9-b0
AuxDAC data (unsigned)
Note: the C-BUS latency period (250µs) should be observed between successive writes to this register.
Note: when $A8 b12 is set to 1, writing data to this register controls the RAMDAC settings. Writing to
AuxDAC1 whilst the RAMDAC is still ramping may cause un-intended operation. In this mode b10 and
b11 are ignored and b9 to b0 perform the following functions:
b9 reserved, clear to 0
b8 reserved, clear to 0
b7 reserved, clear to 0
b6 RAMDAC RAM access, 0 resets the internal RAMDAC address pointer
RAMDAC Scan Time
b5
0
0
0
0
b4
0
0
1
1
b3
0
1
0
1
Divider
1024
512
256
128
64
Time (ms)
10.50
5.25
2.63
1.31
0.66
1
0
0
1
0
1
32
0.33
1
1
0
16
0.16
1
1
1
8
0.08
b2 Scan direction:
b1 Autocycle
b0 RAMDAC start
0 = ramp down
0 = disable
0 = stop
1 = ramp up
1 = continuous ramp up/down
1 = start RAMDAC ramping
To initiate a RAMDAC ramp up write:
$9005
To initiate a RAMDAC ramp down, write: $9001
Note that initiating a RAMDAC scan will automatically bring AuxDAC1 out of powersave. To place
AuxDAC1 back into powersave, it must be written to explicitly. Do NOT change Idle/Rx/Tx mode whilst the
RAMDAC is still ramping.
4
Do NOT write to directly to AuxDAC1 whilst the RAMDAC is in operation. RAMDAC is only available when in Tx mode.
© 2010 CML Microsystems Plc
37
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
