PMR Signalling Processor
CMX881
1.6
C-BUS Register Description
1.6.1
C-BUS Register Summary
C-BUS Write Only Registers
ADDR.
(hex)
$01
Word Size
REGISTER
(bits)
0
C-BUS RESET
ANALOGUE GAIN
SIGNAL ROUTING
$B0
16
16
16
8
$B1
$B2
$B3
$C0
$C1
$C2
$C3
$C7
$C8
$CA
$CB
$CD
$CE
$CF
AUXILIARY ADC THRESHOLDS
AUXILIARY ADC CONTROL
POWER DOWN CONTROL
MODE CONTROL
16
16
16
16
16
16
16
16
16
16
16
AUDIO & CTCSS CONTROL
TX TONE
RESERVED REGISTER ADDRESS
PROGRAMMING REGISTER
TX DATA
RESERVED REGISTER ADDRESS
AUDIO TONE
INTERRUPT MASK
RESERVED REGISTER ADDRESS
The C-BUS addresses $C7, $CB and $CF are allocated for production testing and must not be accessed
in normal operation.
C-BUS Read Only Registers
ADDR
(hex)
$B4
Word Size
REGISTER
(bits)
8
AUXILIARY ADC DATA
RX DATA
$C5
16
$C6
STATUS
16
$C9
RESERVED REGISTER ADDRESS
TONE STATUS
16
$CC
16
Interrupt Operation
The CMX881 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status register and
the IRQ Mask bit (bit 15) are both set to ‘1’. The IRQ bit is set when the state of the interrupt flag bits in
the Status register change from a '0' to a '1' and the corresponding mask bit(s) in the Interrupt Mask
register is(are) set.
All interrupt flag bits in the Status register except the Programming Flag (bit 0) are cleared and the
interrupt request is cleared following the command/address phase of a C-BUS read of the flag register.
The Programming Flag bit is set to '1' only when it is permissible to write a new word to the Programming
register.
2004 CML Microsystems Plc
29
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
