PMR Signalling Processor
CMX881
…
Rx frame example:
BS
BS
FS
FS
0
1
2
3
CS
CS
0
1
2
Rx over air data
Write Mode reg 2
Frame Sync flag
MSK transfer flag
Read Status reg 2
Checksum bit 3
Read Rx Data reg 2
Enable CRC bit 2,1
0
1
2
3
CS
CS
0
1
2
BS = Bit sync
FS = Frame sync
0, 1, … Data bytes CS = Checksum
Notes: 1 The Enable CRC bit is controlled by writing to the Tx Data register
2 Actions requiring a C-BUS transfer
3 The Checksum bit is read from the Rx Data register
1.5.5.1
Tx Hang bit
When transmitting FFSK/MSK data, the user should ensure that the data is terminated with a hang bit.
This is recommended regardless of whether the on-chip data formatting is used. To do this, the host
must set the 'Last Data' bit in the Tx Data register ($CA) when the message is required to end. This will
append a hang bit onto the end of the current byte and generate (if enabled) an interrupt when the last Tx
data has left the modulator.
Write Mode reg 2
MSK transfer flag
Tx MSK end flag
Read Status reg 2
Write Tx Data reg 2
Enable CRC bit 1
Tx CRC bit 1
BS
BS
FS
FS
0
1
2
3
Last Data bit 1
Tx over air data
BS = Bit sync
BS
BS
FS
FS
0
1
2
3
CS
CS
H
FS = Frame sync
0, 1, … Data bytes CS = Checksum
H = Hang Bit
Notes: 1 The Tx CRC, Enable CRC and Last Data bits are changed by writing to the Tx Data
register
2 Actions requiring a C-BUS transfer
1.5.5.2
Data Buffer Timing
Data must be transferred at the rate appropriate to the signal type and data format. The CMX881 buffers
signal data in the lower 8-bits of a 16-bit register. The CMX881 will issue interrupts to indicate when data
is available or required. The host must respond to these interrupts within the maximum allowable latency
for the signal type. Table 9 shows the maximum latencies for transferring signal data to maintain
appropriate data throughput.
Table 9 Maximum Data Transfer Latency
Max time to read from
or write to data buffer
Data buffer
size
Data type
1200b/s MSK
2400b/s MSK
6.6ms
3.3ms
8 bits
8 bits
2004 CML Microsystems Plc
27
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
