PMR Signalling Processor
CMX881
1.5.6
C-BUS Operation
This block provides for the transfer of data and control or status information between the CMX881’s
internal registers and the µC over the C-BUS serial interface. Each transaction consists of a single
Register Address byte sent from the µC which may be followed by one or more data byte(s) sent from the
µC to be written into one of the CMX881’s Write Only Registers, or one or more data byte(s) read out
from one of the CMX881’s Read Only Registers, as illustrated in Figure 12.
Data sent from the µC on the Command Data line is clocked into the CMX881 on the rising edge of the
Serial_Clock input. Reply Data sent from the CMX881 to the µC is valid when the Serial_Clock is high.
The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS
interface is compatible with most common µC serial interfaces and may also be easily implemented with
general purpose µC I/O pins controlled by a simple software routine.
The number of data bytes following an A/C byte is dependent on the value of the A/C byte. The most
significant bit of the address or data are sent first. For detailed timings see section 1.8.1.
C-BUS Write:
See Note 1
See Note 2
CSN
Serial_Clock
CMD_DATA
7
6
5
4
3
2
1
0
7
6
…
0
7
…
0
MSB
LSB
MSB
LSB
MSB
LSB
Address / Command byte
Upper 8 bits
Lower 8 bits
REPLY_DATA
High Z state
C-BUS Read:
CSN
See Note 2
Serial_Clock
CMD_DATA
7
6
5
4
3
2
1
0
MSB
LSB
Address byte
Upper 8 bits
Lower 8 bits
REPLY_DATA
7
6
…
0
7
…
0
High Z state
MSB
LSB
MSB
LSB
Data value unimportant
Repeated cycles
Either logic level valid
Figure 12 C-BUS Transactions
Notes:
1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset).
2. For single byte data transfers only the first 8 bits of the data are transferred.
3. The CMD_DATA and REPLY_DATA lines are never active at the same time. The Address byte
determines the data direction for each C-BUS transfer.
4. The Serial_Clock input can be high or low at the start and end of each C-BUS transaction.
5. The gaps shown between each byte on the CMD_DATA and REPLY_DATA lines in the above
diagram are optional, the host may insert gaps or concatenate the data as required.
2004 CML Microsystems Plc
28
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
