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CMX881 参数 Datasheet PDF下载

CMX881图片预览
型号: CMX881
PDF下载: 下载PDF文件 查看货源
内容描述: 基带处理器的PMR和集群对讲机 [Baseband Processor for PMR and Trunked Radios]
分类和应用: 对讲机
文件页数/大小: 59 页 / 863 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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PMR Signalling Processor  
CMX881  
1.5.4.6  
Transmitting DTMF Tones  
The DTMF signals to be generated are defined in the TX TONE register ($C3). Single tones and twist  
(lower frequency tone reduced by 2dB) can be enabled by setting the appropriate bit in the $C3 register  
to '1'. The DTMF level is set in programming register P1.0. The DTMF tones must be transmitted on  
their own within the voice band, the host µC must disable other voice band signals prior to initiating  
transmission of the DTMF tones, and (if required) restore the voice band signals after the DTMF  
transmission is complete. Table 8 shows the DTMF tone pairs, together with the values for programming  
the ‘Tone Pair’ field of the TX TONE register.  
Table 8 DTMF Tone Pairs and Corresponding Tx Programming Codes  
Tone Pair  
Key Pad  
Low Tone  
(Hz)  
697  
697  
697  
770  
770  
770  
852  
852  
852  
941  
941  
941  
697  
770  
852  
941  
High Tone  
(Hz)  
Code (Hex)  
Position  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
0
*
1209  
1336  
1477  
1209  
1336  
1477  
1209  
1336  
1477  
1336  
1209  
1477  
1633  
1633  
1633  
1633  
#
A
B
C
D
Note: Only the underlined tone is generated when the 'Single Tone' bit is enabled.  
1.5.5  
FFSK/MSK Data packeting  
The CMX881 has a built in 15 bit CRC and 1 bit parity generator / checker to ease host processing during  
transmission and reception of data packets. The CRC / parity function can be used with any length  
message in both Tx and Rx modes. In Tx the host may reset, add to or send the 2 byte checksum at any  
byte boundary in the data sequence. In Rx the host may reset the checking circuit at any byte boundary  
and the CMX881 will indicate for each subsequent byte if the preceding bytes satisfied the CRC and  
parity requirements.  
Tx frame example:  
Write Mode reg 2  
MSK transfer flag  
Read Status reg 2  
Write Tx Data reg 2  
Enable CRC bit 1  
Tx CRC bit 1  
BS  
BS  
FS  
FS  
0
1
2
3
0
1
2
BS  
BS  
FS  
FS  
0
1
2
3
CS  
CS  
0
1
2
Tx over air data  
BS = Bit sync  
FS = Frame sync  
0, 1, … Data bytes CS = Checksum  
Notes: 1 The Tx CRC and Enable CRC bits are controlled by writing to the Tx Data register  
2 Actions requiring a C-BUS transfer  
2004 CML Microsystems Plc  
26  
D/881/7  
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