TDMA Digital Radio Processor
CMX7161
2
Block Diagrams
Receive Functions
Transmit Functions
MOD1P
MOD1N
Channel
Filter
IINPUTP
IINPUTN
Data
Data
Demodulator
Modulator
MOD2P
MOD2N
Channel
Filter
QINPUTP
QINPUTN
RSSI
Auxiliary Functions
I
Thresholds
Averaging
ADC 1
ADC 2
ADC 3
ADC 4
Q
Thresholds
Averaging
IRQN
Tx Data FIFO
Rx Data FIFO
MUX
RDATA
Thresholds
Averaging
CSN
AUXADC1
AUXADC2
AUXADC3
AUXADC4
CDATA
SCLK
Thresholds
Averaging
Registers
Auxiliary Multiplexed ADCs
C-BUS Interface
GPIOA
GPIOB
GPIOC
GPIO with O/P
Sequencer
System Clock Div
1
SYSCLK1
SYSCLK2
System Clock Div 2
GPIOD
FI Configured I/O
System
Clock PLL
Clock
Distribution
DAC 1
DAC 2
DAC 3
DAC 4
Ramp-profile RAM
AUXDAC1
AUXDAC2
AUXDAC3
AUXDAC4
SYSCLKIN
Main
Clock PLL
System Clocks
Power
control
Auxiliary DACs
MOSI
CLK
AGC
Controller
MISO
SPI Thru
Port
Flash Boot
SSOUT0
SSOUT1
Host Thru
Commands
Device
Reset
Boot
Control
SSOUT2
Bias
Reg.
C-BUS/SPI Thru Control
Figure 1 Overall Block Diagram
2013 CML Microsystems Plc
Page 6
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
