TDMA Digital Radio Processor
CMX7161
2
Block Diagrams
Receive Functions
IINPUTP
IINPUTN
Transmit Functions
Data
Demodulator
Data
Modulator
MOD1P
MOD1N
Channel
Filter
Channel
Filter
RSSI
QINPUTP
QINPUTN
MOD2P
MOD2N
Auxiliary Functions
I
Q
ADC 1
Thresholds
Averaging
Thresholds
Averaging
Thresholds
Averaging
Thresholds
Averaging
Registers
Rx Data FIFO
Tx Data FIFO
IRQN
RDATA
CSN
CDATA
SCLK
ADC 2
MUX
AUXADC1
AUXADC2
AUXADC3
AUXADC4
ADC 4
ADC 3
Auxiliary Multiplexed ADCs
C-BUS Interface
GPIOA
GPIOB
GPIOC
GPIOD
GPIO with O/P
Sequencer
System Clock Div 1
System Clock Div 2
SYSCLK1
SYSCLK2
FI Configured I/O
System
Clock PLL
Main
Clock PLL
AUXDAC1
AUXDAC2
AUXDAC3
AUXDAC4
DAC 1
DAC 2
DAC 3
DAC 4
Ramp-profile RAM
Clock
Distribution
SYSCLKIN
System Clocks
Auxiliary DACs
Power
control
MOSI
CLK
MISO
SPI Thru
Port
SSOUT0
SSOUT1
SSOUT2
AGC
Controller
Flash Boot
Host Thru
Commands
Device
Reset
Bias
Reg.
C-BUS/SPI Thru Control
Boot
Control
DVDD
Figure 1 Overall Block Diagram
2013 CML Microsystems Plc
Page 6
BOOTEN1
BOOTEN2
DVCORE
RESETN
VBIAS
ADCREF
DVSS
AVSS
DACREF
AVDD
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
