TDMA Digital Radio Processor
CMX7161
7.10.2 Auxiliary ADC Operation ...................................................................................... 28
7.10.3 Auxiliary DAC/RAMDAC Operation...................................................................... 29
7.10.4 SPI Thru-Port ....................................................................................................... 29
7.11
7.12
Digital System Clock Generators................................................................................ 29
C-BUS Register Summary.......................................................................................... 31
8
Performance Specification ................................................................................................... 32
8.1
Electrical Performance ............................................................................................... 32
8.1.1 Absolute Maximum Ratings ................................................................................. 32
8.1.2 Operating Limits................................................................................................... 32
8.1.3 Operating Characteristics..................................................................................... 33
8.1.4 Parametric Performance...................................................................................... 38
C-BUS Timing............................................................................................................. 39
Packaging................................................................................................................... 40
8.2
8.3
Table
Page
Table 1 Definition of Power Supply and Reference Voltages........................................................ 10
Table 2 BOOTEN Pin States......................................................................................................... 18
Table 3 C-BUS Registers.............................................................................................................. 31
Figure
Page
Figure 1 Overall Block Diagram ...................................................................................................... 6
Figure 2 Signal Flow: Two-point Tx with I/Q Rx .............................................................................. 7
Figure 3 CMX7161 Power Supply and De-coupling...................................................................... 11
Figure 4 Recommended External Components – System Clock Interface................................... 12
Figure 5 Recommended External Components – C-BUS Interface.............................................. 12
Figure 6 Recommended External Components – 2-Point Output Reconstruction Filter............... 13
Figure 7 Outline Radio Design ...................................................................................................... 15
Figure 8 Basic C-BUS Transactions ............................................................................................. 16
Figure 9 C-BUS Data Streaming Operation.................................................................................. 17
Figure 10 FI Loading from Host .................................................................................................... 19
Figure 11 FI Loading from Serial Memory..................................................................................... 20
Figure 12 Tx Spectrum and Modulation Measurement Configuration for Two-point Modulation.. 22
Figure 13 Tx Modulation Spectra (4-FSK, 9.6kbps, RRC – 0.2)................................................... 23
Figure 14 Slot Structure ................................................................................................................ 24
Figure 15 Timing relationships...................................................................................................... 25
Figure 16 Received Eye Diagram ................................................................................................. 26
Figure 17 Digital System Clock Generation Schemes .................................................................. 30
Figure 18 C-BUS Timing............................................................................................................... 39
Figure 19 Mechanical Outline of 64-lead VQFN (Q1) ................................................................... 40
Figure 20 Mechanical Outline of 64-pin LQFP (L9)....................................................................... 40
Information in this datasheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version on the CML website: [www.cmlmicro.com].
2013 CML Microsystems Plc
Page 4
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
